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-rw-r--r--deps/v8/src/s390/assembler-s390.cc603
1 files changed, 59 insertions, 544 deletions
diff --git a/deps/v8/src/s390/assembler-s390.cc b/deps/v8/src/s390/assembler-s390.cc
index a448947307..448acb34ad 100644
--- a/deps/v8/src/s390/assembler-s390.cc
+++ b/deps/v8/src/s390/assembler-s390.cc
@@ -138,39 +138,48 @@ void CpuFeatures::ProbeImpl(bool cross_compile) {
// The facilities we are checking for are:
// Bit 45 - Distinct Operands for instructions like ARK, SRK, etc.
// As such, we require only 1 double word
- int64_t facilities[1];
- facilities[0] = 0;
+ int64_t facilities[3] = {0L};
// LHI sets up GPR0
// STFLE is specified as .insn, as opcode is not recognized.
// We register the instructions kill r0 (LHI) and the CC (STFLE).
asm volatile(
- "lhi 0,0\n"
+ "lhi 0,2\n"
".insn s,0xb2b00000,%0\n"
: "=Q"(facilities)
:
: "cc", "r0");
+ uint64_t one = static_cast<uint64_t>(1);
// Test for Distinct Operands Facility - Bit 45
- if (facilities[0] & (1lu << (63 - 45))) {
+ if (facilities[0] & (one << (63 - 45))) {
supported_ |= (1u << DISTINCT_OPS);
}
// Test for General Instruction Extension Facility - Bit 34
- if (facilities[0] & (1lu << (63 - 34))) {
+ if (facilities[0] & (one << (63 - 34))) {
supported_ |= (1u << GENERAL_INSTR_EXT);
}
// Test for Floating Point Extension Facility - Bit 37
- if (facilities[0] & (1lu << (63 - 37))) {
+ if (facilities[0] & (one << (63 - 37))) {
supported_ |= (1u << FLOATING_POINT_EXT);
}
+ // Test for Vector Facility - Bit 129
+ if (facilities[2] & (one << (63 - (129 - 128)))) {
+ supported_ |= (1u << VECTOR_FACILITY);
+ }
+ // Test for Miscellaneous Instruction Extension Facility - Bit 58
+ if (facilities[0] & (1lu << (63 - 58))) {
+ supported_ |= (1u << MISC_INSTR_EXT2);
+ }
}
#else
// All distinct ops instructions can be simulated
supported_ |= (1u << DISTINCT_OPS);
// RISBG can be simulated
supported_ |= (1u << GENERAL_INSTR_EXT);
-
supported_ |= (1u << FLOATING_POINT_EXT);
+ supported_ |= (1u << MISC_INSTR_EXT2);
USE(performSTFLE); // To avoid assert
+ supported_ |= (1u << VECTOR_FACILITY);
#endif
supported_ |= (1u << FPU);
}
@@ -192,6 +201,8 @@ void CpuFeatures::PrintFeatures() {
printf("FPU_EXT=%d\n", CpuFeatures::IsSupported(FLOATING_POINT_EXT));
printf("GENERAL_INSTR=%d\n", CpuFeatures::IsSupported(GENERAL_INSTR_EXT));
printf("DISTINCT_OPS=%d\n", CpuFeatures::IsSupported(DISTINCT_OPS));
+ printf("VECTOR_FACILITY=%d\n", CpuFeatures::IsSupported(VECTOR_FACILITY));
+ printf("MISC_INSTR_EXT2=%d\n", CpuFeatures::IsSupported(MISC_INSTR_EXT2));
}
Register ToRegister(int num) {
@@ -233,13 +244,19 @@ Address RelocInfo::wasm_global_reference() {
return Assembler::target_address_at(pc_, host_);
}
+uint32_t RelocInfo::wasm_function_table_size_reference() {
+ DCHECK(IsWasmFunctionTableSizeReference(rmode_));
+ return static_cast<uint32_t>(
+ reinterpret_cast<intptr_t>(Assembler::target_address_at(pc_, host_)));
+}
+
void RelocInfo::unchecked_update_wasm_memory_reference(
Address address, ICacheFlushMode flush_mode) {
Assembler::set_target_address_at(isolate_, pc_, host_, address, flush_mode);
}
-void RelocInfo::unchecked_update_wasm_memory_size(uint32_t size,
- ICacheFlushMode flush_mode) {
+void RelocInfo::unchecked_update_wasm_size(uint32_t size,
+ ICacheFlushMode flush_mode) {
Assembler::set_target_address_at(isolate_, pc_, host_,
reinterpret_cast<Address>(size), flush_mode);
}
@@ -522,11 +539,11 @@ void Assembler::load_label_offset(Register r1, Label* L) {
// Pseudo op - branch on condition
void Assembler::branchOnCond(Condition c, int branch_offset, bool is_bound) {
- int offset = branch_offset;
- if (is_bound && is_int16(offset)) {
- brc(c, Operand(offset & 0xFFFF)); // short jump
+ int offset_in_halfwords = branch_offset / 2;
+ if (is_bound && is_int16(offset_in_halfwords)) {
+ brc(c, Operand(offset_in_halfwords & 0xFFFF)); // short jump
} else {
- brcl(c, Operand(offset)); // long jump
+ brcl(c, Operand(offset_in_halfwords)); // long jump
}
}
@@ -580,38 +597,6 @@ void Assembler::nop(int type) {
}
}
-// RR format: <insn> R1,R2
-// +--------+----+----+
-// | OpCode | R1 | R2 |
-// +--------+----+----+
-// 0 8 12 15
-#define RR_FORM_EMIT(name, op) \
- void Assembler::name(Register r1, Register r2) { rr_form(op, r1, r2); }
-
-void Assembler::rr_form(Opcode op, Register r1, Register r2) {
- DCHECK(is_uint8(op));
- emit2bytes(op * B8 | r1.code() * B4 | r2.code());
-}
-
-void Assembler::rr_form(Opcode op, DoubleRegister r1, DoubleRegister r2) {
- DCHECK(is_uint8(op));
- emit2bytes(op * B8 | r1.code() * B4 | r2.code());
-}
-
-// RR2 format: <insn> M1,R2
-// +--------+----+----+
-// | OpCode | M1 | R2 |
-// +--------+----+----+
-// 0 8 12 15
-#define RR2_FORM_EMIT(name, op) \
- void Assembler::name(Condition m1, Register r2) { rr_form(op, m1, r2); }
-
-void Assembler::rr_form(Opcode op, Condition m1, Register r2) {
- DCHECK(is_uint8(op));
- DCHECK(is_uint4(m1));
- emit2bytes(op * B8 | m1 * B4 | r2.code());
-}
-
// RX format: <insn> R1,D2(X2,B2)
// +--------+----+----+----+-------------+
// | OpCode | R1 | X2 | B2 | D2 |
@@ -716,75 +701,6 @@ void Assembler::rie_form(Opcode op, Register r1, Register r3,
emit6bytes(code);
}
-// RIL1 format: <insn> R1,I2
-// +--------+----+----+------------------------------------+
-// | OpCode | R1 |OpCd| I2 |
-// +--------+----+----+------------------------------------+
-// 0 8 12 16 47
-#define RIL1_FORM_EMIT(name, op) \
- void Assembler::name(Register r, const Operand& i2) { ril_form(op, r, i2); }
-
-void Assembler::ril_form(Opcode op, Register r1, const Operand& i2) {
- DCHECK(is_uint12(op));
- uint64_t code = (static_cast<uint64_t>(op & 0xFF0)) * B36 |
- (static_cast<uint64_t>(r1.code())) * B36 |
- (static_cast<uint64_t>(op & 0x00F)) * B32 |
- (static_cast<uint64_t>(i2.imm_) & 0xFFFFFFFF);
- emit6bytes(code);
-}
-
-// RIL2 format: <insn> M1,I2
-// +--------+----+----+------------------------------------+
-// | OpCode | M1 |OpCd| I2 |
-// +--------+----+----+------------------------------------+
-// 0 8 12 16 47
-#define RIL2_FORM_EMIT(name, op) \
- void Assembler::name(Condition m1, const Operand& i2) { \
- ril_form(op, m1, i2); \
- }
-
-void Assembler::ril_form(Opcode op, Condition m1, const Operand& i2) {
- DCHECK(is_uint12(op));
- DCHECK(is_uint4(m1));
- uint64_t code = (static_cast<uint64_t>(op & 0xFF0)) * B36 |
- (static_cast<uint64_t>(m1)) * B36 |
- (static_cast<uint64_t>(op & 0x00F)) * B32 |
- (static_cast<uint64_t>(i2.imm_ & 0xFFFFFFFF));
- emit6bytes(code);
-}
-
-// RRE format: <insn> R1,R2
-// +------------------+--------+----+----+
-// | OpCode |////////| R1 | R2 |
-// +------------------+--------+----+----+
-// 0 16 24 28 31
-#define RRE_FORM_EMIT(name, op) \
- void Assembler::name(Register r1, Register r2) { rre_form(op, r1, r2); }
-
-void Assembler::rre_form(Opcode op, Register r1, Register r2) {
- DCHECK(is_uint16(op));
- emit4bytes(op << 16 | r1.code() * B4 | r2.code());
-}
-
-void Assembler::rre_form(Opcode op, DoubleRegister r1, DoubleRegister r2) {
- DCHECK(is_uint16(op));
- emit4bytes(op << 16 | r1.code() * B4 | r2.code());
-}
-
-// RRD format: <insn> R1,R3, R2
-// +------------------+----+----+----+----+
-// | OpCode | R1 |////| R3 | R2 |
-// +------------------+----+----+----+----+
-// 0 16 20 24 28 31
-#define RRD_FORM_EMIT(name, op) \
- void Assembler::name(Register r1, Register r3, Register r2) { \
- rrd_form(op, r1, r3, r2); \
- }
-
-void Assembler::rrd_form(Opcode op, Register r1, Register r3, Register r2) {
- emit4bytes(op << 16 | r1.code() * B12 | r3.code() * B4 | r2.code());
-}
-
// RS1 format: <insn> R1,R3,D2(B2)
// +--------+----+----+----+-------------+
// | OpCode | R1 | R3 | B2 | D2 |
@@ -1104,7 +1020,7 @@ void Assembler::si_form(Opcode op, const Operand& i2, Register b1, Disp d1) {
}
void Assembler::siy_form(Opcode op, const Operand& i2, Register b1, Disp d1) {
- DCHECK(is_uint20(d1));
+ DCHECK(is_uint20(d1) || is_int20(d1));
DCHECK(is_uint16(op));
DCHECK(is_uint8(i2.imm_));
uint64_t code = (static_cast<uint64_t>(op & 0xFF00)) * B32 |
@@ -1418,46 +1334,28 @@ void Assembler::rrfe_form(Opcode op, Condition m3, Condition m4, Register r1,
// start of S390 instruction
RX_FORM_EMIT(bc, BC)
-RR_FORM_EMIT(bctr, BCTR)
RXE_FORM_EMIT(ceb, CEB)
SS1_FORM_EMIT(ed, ED)
RX_FORM_EMIT(ex, EX)
-RRE_FORM_EMIT(flogr, FLOGR)
-RRE_FORM_EMIT(lcgr, LCGR)
-RR_FORM_EMIT(lcr, LCR)
RX_FORM_EMIT(le_z, LE)
RXY_FORM_EMIT(ley, LEY)
-RIL1_FORM_EMIT(llihf, LLIHF)
-RIL1_FORM_EMIT(llilf, LLILF)
-RRE_FORM_EMIT(lngr, LNGR)
-RR_FORM_EMIT(lnr, LNR)
-RRE_FORM_EMIT(lrvr, LRVR)
-RRE_FORM_EMIT(lrvgr, LRVGR)
RXY_FORM_EMIT(lrv, LRV)
RXY_FORM_EMIT(lrvg, LRVG)
RXY_FORM_EMIT(lrvh, LRVH)
SS1_FORM_EMIT(mvn, MVN)
SS1_FORM_EMIT(nc, NC)
SI_FORM_EMIT(ni, NI)
-RIL1_FORM_EMIT(nihf, NIHF)
-RIL1_FORM_EMIT(nilf, NILF)
RI1_FORM_EMIT(nilh, NILH)
RI1_FORM_EMIT(nill, NILL)
-RIL1_FORM_EMIT(oihf, OIHF)
-RIL1_FORM_EMIT(oilf, OILF)
RI1_FORM_EMIT(oill, OILL)
-RRE_FORM_EMIT(popcnt, POPCNT_Z)
-RIL1_FORM_EMIT(slfi, SLFI)
+RXY_FORM_EMIT(pfd, PFD)
RXY_FORM_EMIT(slgf, SLGF)
-RIL1_FORM_EMIT(slgfi, SLGFI)
RXY_FORM_EMIT(strvh, STRVH)
RXY_FORM_EMIT(strv, STRV)
RXY_FORM_EMIT(strvg, STRVG)
RI1_FORM_EMIT(tmll, TMLL)
SS1_FORM_EMIT(tr, TR)
S_FORM_EMIT(ts, TS)
-RIL1_FORM_EMIT(xihf, XIHF)
-RIL1_FORM_EMIT(xilf, XILF)
// -------------------------
// Load Address Instructions
@@ -1473,11 +1371,6 @@ void Assembler::lay(Register r1, const MemOperand& opnd) {
}
// Load Address Relative Long
-void Assembler::larl(Register r1, const Operand& opnd) {
- ril_form(LARL, r1, opnd);
-}
-
-// Load Address Relative Long
void Assembler::larl(Register r1, Label* l) {
larl(r1, Operand(branch_offset(l)));
}
@@ -1490,17 +1383,11 @@ void Assembler::lb(Register r, const MemOperand& src) {
rxy_form(LB, r, src.rx(), src.rb(), src.offset());
}
-// Load Byte Register-Register (32<-8)
-void Assembler::lbr(Register r1, Register r2) { rre_form(LBR, r1, r2); }
-
// Load Byte Register-Storage (64<-8)
void Assembler::lgb(Register r, const MemOperand& src) {
rxy_form(LGB, r, src.rx(), src.rb(), src.offset());
}
-// Load Byte Register-Register (64<-8)
-void Assembler::lgbr(Register r1, Register r2) { rre_form(LGBR, r1, r2); }
-
// Load Halfword Register-Storage (32<-16)
void Assembler::lh(Register r, const MemOperand& src) {
rx_form(LH, r, src.rx(), src.rb(), src.offset());
@@ -1511,17 +1398,11 @@ void Assembler::lhy(Register r, const MemOperand& src) {
rxy_form(LHY, r, src.rx(), src.rb(), src.offset());
}
-// Load Halfword Register-Register (32<-16)
-void Assembler::lhr(Register r1, Register r2) { rre_form(LHR, r1, r2); }
-
// Load Halfword Register-Storage (64<-16)
void Assembler::lgh(Register r, const MemOperand& src) {
rxy_form(LGH, r, src.rx(), src.rb(), src.offset());
}
-// Load Halfword Register-Register (64<-16)
-void Assembler::lghr(Register r1, Register r2) { rre_form(LGHR, r1, r2); }
-
// Load Register-Storage (32)
void Assembler::l(Register r, const MemOperand& src) {
rx_form(L, r, src.rx(), src.rb(), src.offset());
@@ -1532,25 +1413,16 @@ void Assembler::ly(Register r, const MemOperand& src) {
rxy_form(LY, r, src.rx(), src.rb(), src.offset());
}
-// Load Register-Register (32)
-void Assembler::lr(Register r1, Register r2) { rr_form(LR, r1, r2); }
-
// Load Register-Storage (64)
void Assembler::lg(Register r, const MemOperand& src) {
rxy_form(LG, r, src.rx(), src.rb(), src.offset());
}
-// Load Register-Register (64)
-void Assembler::lgr(Register r1, Register r2) { rre_form(LGR, r1, r2); }
-
// Load Register-Storage (64<-32)
void Assembler::lgf(Register r, const MemOperand& src) {
rxy_form(LGF, r, src.rx(), src.rb(), src.offset());
}
-// Load Sign Extended Register-Register (64<-32)
-void Assembler::lgfr(Register r1, Register r2) { rre_form(LGFR, r1, r2); }
-
// Load Halfword Immediate (32)
void Assembler::lhi(Register r, const Operand& imm) { ri_form(LHI, r, imm); }
@@ -1570,15 +1442,6 @@ void Assembler::ltg(Register r1, const MemOperand& opnd) {
rxy_form(LTG, r1, opnd.rx(), opnd.rb(), opnd.offset());
}
-// Load and Test Register-Register (32)
-void Assembler::ltr(Register r1, Register r2) { rr_form(LTR, r1, r2); }
-
-// Load and Test Register-Register (64)
-void Assembler::ltgr(Register r1, Register r2) { rre_form(LTGR, r1, r2); }
-
-// Load and Test Register-Register (64<-32)
-void Assembler::ltgfr(Register r1, Register r2) { rre_form(LTGFR, r1, r2); }
-
// -------------------------
// Load Logical Instructions
// -------------------------
@@ -1597,9 +1460,6 @@ void Assembler::llgf(Register r1, const MemOperand& opnd) {
rxy_form(LLGF, r1, opnd.rx(), opnd.rb(), opnd.offset());
}
-// Load Logical Register-Register (64<-32)
-void Assembler::llgfr(Register r1, Register r2) { rre_form(LLGFR, r1, r2); }
-
// Load Logical halfword Register-Storage (32)
void Assembler::llh(Register r1, const MemOperand& opnd) {
rxy_form(LLH, r1, opnd.rx(), opnd.rb(), opnd.offset());
@@ -1610,12 +1470,6 @@ void Assembler::llgh(Register r1, const MemOperand& opnd) {
rxy_form(LLGH, r1, opnd.rx(), opnd.rb(), opnd.offset());
}
-// Load Logical halfword Register-Register (32)
-void Assembler::llhr(Register r1, Register r2) { rre_form(LLHR, r1, r2); }
-
-// Load Logical halfword Register-Register (64)
-void Assembler::llghr(Register r1, Register r2) { rre_form(LLGHR, r1, r2); }
-
// Load On Condition R-R (32)
void Assembler::locr(Condition m3, Register r1, Register r2) {
rrf2_form(LOCR << 16 | m3 * B12 | r1.code() * B4 | r2.code());
@@ -1639,11 +1493,6 @@ void Assembler::locg(Condition m3, Register r1, const MemOperand& src) {
// -------------------
// Branch Instructions
// -------------------
-// Branch and Save
-void Assembler::basr(Register r1, Register r2) { rr_form(BASR, r1, r2); }
-
-// Indirect Conditional Branch via register
-void Assembler::bcr(Condition m, Register target) { rr_form(BCR, m, target); }
// Branch on Count (32)
void Assembler::bct(Register r, const MemOperand& opnd) {
@@ -1660,31 +1509,8 @@ void Assembler::bras(Register r, const Operand& opnd) {
ri_form(BRAS, r, opnd);
}
-// Branch Relative and Save (64)
-void Assembler::brasl(Register r, const Operand& opnd) {
- ril_form(BRASL, r, opnd);
-}
-
// Branch relative on Condition (32)
-void Assembler::brc(Condition c, const Operand& opnd) {
- // BRC actually encodes # of halfwords, so divide by 2.
- int16_t numHalfwords = static_cast<int16_t>(opnd.immediate()) / 2;
- Operand halfwordOp = Operand(numHalfwords);
- halfwordOp.setBits(16);
- ri_form(BRC, c, halfwordOp);
-}
-
-// Branch Relative on Condition (64)
-void Assembler::brcl(Condition c, const Operand& opnd, bool isCodeTarget) {
- Operand halfwordOp = opnd;
- // Operand for code targets will be index to code_targets_
- if (!isCodeTarget) {
- // BRCL actually encodes # of halfwords, so divide by 2.
- int32_t numHalfwords = static_cast<int32_t>(opnd.immediate()) / 2;
- halfwordOp = Operand(numHalfwords);
- }
- ril_form(BRCL, c, halfwordOp);
-}
+void Assembler::brc(Condition c, const Operand& opnd) { ri_form(BRC, c, opnd); }
// Branch On Count (32)
void Assembler::brct(Register r1, const Operand& imm) {
@@ -1717,17 +1543,11 @@ void Assembler::cy(Register r, const MemOperand& opnd) {
rxy_form(CY, r, opnd.rx(), opnd.rb(), opnd.offset());
}
-// Compare Register-Register (32)
-void Assembler::cr_z(Register r1, Register r2) { rr_form(CR, r1, r2); }
-
// Compare Register-Storage (64)
void Assembler::cg(Register r, const MemOperand& opnd) {
rxy_form(CG, r, opnd.rx(), opnd.rb(), opnd.offset());
}
-// Compare Register-Register (64)
-void Assembler::cgr(Register r1, Register r2) { rre_form(CGR, r1, r2); }
-
// Compare Halfword Register-Storage (32)
void Assembler::ch(Register r, const MemOperand& opnd) {
rx_form(CH, r, opnd.rx(), opnd.rb(), opnd.offset());
@@ -1746,14 +1566,6 @@ void Assembler::cghi(Register r, const Operand& opnd) {
ri_form(CGHI, r, opnd);
}
-// Compare Immediate (32)
-void Assembler::cfi(Register r, const Operand& opnd) { ril_form(CFI, r, opnd); }
-
-// Compare Immediate (64)
-void Assembler::cgfi(Register r, const Operand& opnd) {
- ril_form(CGFI, r, opnd);
-}
-
// ----------------------------
// Compare Logical Instructions
// ----------------------------
@@ -1767,25 +1579,11 @@ void Assembler::cly(Register r, const MemOperand& opnd) {
rxy_form(CLY, r, opnd.rx(), opnd.rb(), opnd.offset());
}
-// Compare Logical Register-Register (32)
-void Assembler::clr(Register r1, Register r2) { rr_form(CLR, r1, r2); }
-
// Compare Logical Register-Storage (64)
void Assembler::clg(Register r, const MemOperand& opnd) {
rxy_form(CLG, r, opnd.rx(), opnd.rb(), opnd.offset());
}
-// Compare Logical Register-Register (64)
-void Assembler::clgr(Register r1, Register r2) { rre_form(CLGR, r1, r2); }
-
-// Compare Logical Immediate (32)
-void Assembler::clfi(Register r1, const Operand& i2) { ril_form(CLFI, r1, i2); }
-
-// Compare Logical Immediate (64<32)
-void Assembler::clgfi(Register r1, const Operand& i2) {
- ril_form(CLGFI, r1, i2);
-}
-
// Compare Immediate (Mem - Imm) (8)
void Assembler::cli(const MemOperand& opnd, const Operand& imm) {
si_form(CLI, imm, opnd.rb(), opnd.offset());
@@ -1866,11 +1664,6 @@ void Assembler::ay(Register r1, const MemOperand& opnd) {
rxy_form(AY, r1, opnd.rx(), opnd.rb(), opnd.offset());
}
-// Add Immediate (32)
-void Assembler::afi(Register r1, const Operand& opnd) {
- ril_form(AFI, r1, opnd);
-}
-
// Add Halfword Register-Storage (32)
void Assembler::ah(Register r1, const MemOperand& opnd) {
rx_form(AH, r1, opnd.rx(), opnd.rb(), opnd.offset());
@@ -1889,9 +1682,6 @@ void Assembler::ahik(Register r1, Register r3, const Operand& i2) {
rie_form(AHIK, r1, r3, i2);
}
-// Add Register (32)
-void Assembler::ar(Register r1, Register r2) { rr_form(AR, r1, r2); }
-
// Add Register-Register-Register (32)
void Assembler::ark(Register r1, Register r2, Register r3) {
rrf1_form(ARK, r1, r2, r3);
@@ -1917,14 +1707,6 @@ void Assembler::agf(Register r1, const MemOperand& opnd) {
rxy_form(AGF, r1, opnd.rx(), opnd.rb(), opnd.offset());
}
-// Add Immediate (64)
-void Assembler::agfi(Register r1, const Operand& opnd) {
- ril_form(AGFI, r1, opnd);
-}
-
-// Add Register-Register (64<-32)
-void Assembler::agfr(Register r1, Register r2) { rre_form(AGFR, r1, r2); }
-
// Add Halfword Immediate (64)
void Assembler::aghi(Register r1, const Operand& i2) { ri_form(AGHI, r1, i2); }
@@ -1933,9 +1715,6 @@ void Assembler::aghik(Register r1, Register r3, const Operand& i2) {
rie_form(AGHIK, r1, r3, i2);
}
-// Add Register (64)
-void Assembler::agr(Register r1, Register r2) { rre_form(AGR, r1, r2); }
-
// Add Register-Register-Register (64)
void Assembler::agrk(Register r1, Register r2, Register r3) {
rrf1_form(AGRK, r1, r2, r3);
@@ -1961,17 +1740,6 @@ void Assembler::aly(Register r1, const MemOperand& opnd) {
rxy_form(ALY, r1, opnd.rx(), opnd.rb(), opnd.offset());
}
-// Add Logical Immediate (32)
-void Assembler::alfi(Register r1, const Operand& opnd) {
- ril_form(ALFI, r1, opnd);
-}
-
-// Add Logical Register-Register (32)
-void Assembler::alr(Register r1, Register r2) { rr_form(ALR, r1, r2); }
-
-// Add Logical With Carry Register-Register (32)
-void Assembler::alcr(Register r1, Register r2) { rre_form(ALCR, r1, r2); }
-
// Add Logical Register-Register-Register (32)
void Assembler::alrk(Register r1, Register r2, Register r3) {
rrf1_form(ALRK, r1, r2, r3);
@@ -1985,14 +1753,6 @@ void Assembler::alg(Register r1, const MemOperand& opnd) {
rxy_form(ALG, r1, opnd.rx(), opnd.rb(), opnd.offset());
}
-// Add Logical Immediate (64)
-void Assembler::algfi(Register r1, const Operand& opnd) {
- ril_form(ALGFI, r1, opnd);
-}
-
-// Add Logical Register-Register (64)
-void Assembler::algr(Register r1, Register r2) { rre_form(ALGR, r1, r2); }
-
// Add Logical Register-Register-Register (64)
void Assembler::algrk(Register r1, Register r2, Register r3) {
rrf1_form(ALGRK, r1, r2, r3);
@@ -2021,9 +1781,6 @@ void Assembler::shy(Register r1, const MemOperand& opnd) {
rxy_form(SHY, r1, opnd.rx(), opnd.rb(), opnd.offset());
}
-// Subtract Register (32)
-void Assembler::sr(Register r1, Register r2) { rr_form(SR, r1, r2); }
-
// Subtract Register-Register-Register (32)
void Assembler::srk(Register r1, Register r2, Register r3) {
rrf1_form(SRK, r1, r2, r3);
@@ -2042,12 +1799,6 @@ void Assembler::sgf(Register r1, const MemOperand& opnd) {
rxy_form(SGF, r1, opnd.rx(), opnd.rb(), opnd.offset());
}
-// Subtract Register (64)
-void Assembler::sgr(Register r1, Register r2) { rre_form(SGR, r1, r2); }
-
-// Subtract Register (64<-32)
-void Assembler::sgfr(Register r1, Register r2) { rre_form(SGFR, r1, r2); }
-
// Subtract Register-Register-Register (64)
void Assembler::sgrk(Register r1, Register r2, Register r3) {
rrf1_form(SGRK, r1, r2, r3);
@@ -2066,12 +1817,6 @@ void Assembler::sly(Register r1, const MemOperand& opnd) {
rxy_form(SLY, r1, opnd.rx(), opnd.rb(), opnd.offset());
}
-// Subtract Logical Register-Register (32)
-void Assembler::slr(Register r1, Register r2) { rr_form(SLR, r1, r2); }
-
-// Subtract Logical With Borrow Register-Register (32)
-void Assembler::slbr(Register r1, Register r2) { rre_form(SLBR, r1, r2); }
-
// Subtract Logical Register-Register-Register (32)
void Assembler::slrk(Register r1, Register r2, Register r3) {
rrf1_form(SLRK, r1, r2, r3);
@@ -2085,9 +1830,6 @@ void Assembler::slg(Register r1, const MemOperand& opnd) {
rxy_form(SLG, r1, opnd.rx(), opnd.rb(), opnd.offset());
}
-// Subtract Logical Register-Register (64)
-void Assembler::slgr(Register r1, Register r2) { rre_form(SLGR, r1, r2); }
-
// Subtract Logical Register-Register-Register (64)
void Assembler::slgrk(Register r1, Register r2, Register r3) {
rrf1_form(SLGRK, r1, r2, r3);
@@ -2107,23 +1849,11 @@ void Assembler::mfy(Register r1, const MemOperand& opnd) {
rxy_form(MFY, r1, opnd.rx(), opnd.rb(), opnd.offset());
}
-// Multiply Register (64<32)
-void Assembler::mr_z(Register r1, Register r2) {
- DCHECK(r1.code() % 2 == 0);
- rr_form(MR, r1, r2);
-}
-
// Multiply Logical Register-Storage (64<32)
void Assembler::ml(Register r1, const MemOperand& opnd) {
rxy_form(ML, r1, opnd.rx(), opnd.rb(), opnd.offset());
}
-// Multiply Logical Register (64<32)
-void Assembler::mlr(Register r1, Register r2) {
- DCHECK(r1.code() % 2 == 0);
- rre_form(MLR, r1, r2);
-}
-
// Multiply Single Register-Storage (32)
void Assembler::ms(Register r1, const MemOperand& opnd) {
rx_form(MS, r1, opnd.rx(), opnd.rb(), opnd.offset());
@@ -2134,14 +1864,6 @@ void Assembler::msy(Register r1, const MemOperand& opnd) {
rxy_form(MSY, r1, opnd.rx(), opnd.rb(), opnd.offset());
}
-// Multiply Single Immediate (32)
-void Assembler::msfi(Register r1, const Operand& opnd) {
- ril_form(MSFI, r1, opnd);
-}
-
-// Multiply Single Register (64<32)
-void Assembler::msr(Register r1, Register r2) { rre_form(MSR, r1, r2); }
-
// Multiply Halfword Register-Storage (32)
void Assembler::mh(Register r1, const MemOperand& opnd) {
rx_form(MH, r1, opnd.rx(), opnd.rb(), opnd.offset());
@@ -2157,6 +1879,16 @@ void Assembler::mhi(Register r1, const Operand& opnd) {
ri_form(MHI, r1, opnd);
}
+// Multiply Single Register (32)
+void Assembler::msrkc(Register r1, Register r2, Register r3) {
+ rrf1_form(MSRKC, r1, r2, r3);
+}
+
+// Multiply Single Register (64)
+void Assembler::msgrkc(Register r1, Register r2, Register r3) {
+ rrf1_form(MSGRKC, r1, r2, r3);
+}
+
// ----------------------------
// 64-bit Multiply Instructions
// ----------------------------
@@ -2165,27 +1897,16 @@ void Assembler::mlg(Register r1, const MemOperand& opnd) {
rxy_form(MLG, r1, opnd.rx(), opnd.rb(), opnd.offset());
}
-// Multiply Register (128<64)
-void Assembler::mlgr(Register r1, Register r2) { rre_form(MLGR, r1, r2); }
-
// Multiply Halfword Immediate (64)
void Assembler::mghi(Register r1, const Operand& opnd) {
ri_form(MGHI, r1, opnd);
}
-// Multiply Single Immediate (64)
-void Assembler::msgfi(Register r1, const Operand& opnd) {
- ril_form(MSGFI, r1, opnd);
-}
-
// Multiply Single Register-Storage (64)
void Assembler::msg(Register r1, const MemOperand& opnd) {
rxy_form(MSG, r1, opnd.rx(), opnd.rb(), opnd.offset());
}
-// Multiply Single Register-Register (64)
-void Assembler::msgr(Register r1, Register r2) { rre_form(MSGR, r1, r2); }
-
// --------------------------
// 32-bit Divide Instructions
// --------------------------
@@ -2194,29 +1915,11 @@ void Assembler::d(Register r1, const MemOperand& opnd) {
rx_form(D, r1, opnd.rx(), opnd.rb(), opnd.offset());
}
-// Divide Register (32<-64)
-void Assembler::dr(Register r1, Register r2) {
- DCHECK(r1.code() % 2 == 0);
- rr_form(DR, r1, r2);
-}
-
// Divide Logical Register-Storage (32<-64)
void Assembler::dl(Register r1, const MemOperand& opnd) {
rx_form(DL, r1, opnd.rx(), opnd.rb(), opnd.offset());
}
-// Divide Logical Register (32<-64)
-void Assembler::dlr(Register r1, Register r2) { rre_form(DLR, r1, r2); }
-
-// --------------------------
-// 64-bit Divide Instructions
-// --------------------------
-// Divide Logical Register (64<-128)
-void Assembler::dlgr(Register r1, Register r2) { rre_form(DLGR, r1, r2); }
-
-// Divide Single Register (64<-32)
-void Assembler::dsgr(Register r1, Register r2) { rre_form(DSGR, r1, r2); }
-
// --------------------
// Bitwise Instructions
// --------------------
@@ -2230,9 +1933,6 @@ void Assembler::ny(Register r1, const MemOperand& opnd) {
rxy_form(NY, r1, opnd.rx(), opnd.rb(), opnd.offset());
}
-// AND Register (32)
-void Assembler::nr(Register r1, Register r2) { rr_form(NR, r1, r2); }
-
// AND Register-Register-Register (32)
void Assembler::nrk(Register r1, Register r2, Register r3) {
rrf1_form(NRK, r1, r2, r3);
@@ -2243,9 +1943,6 @@ void Assembler::ng(Register r1, const MemOperand& opnd) {
rxy_form(NG, r1, opnd.rx(), opnd.rb(), opnd.offset());
}
-// AND Register (64)
-void Assembler::ngr(Register r1, Register r2) { rre_form(NGR, r1, r2); }
-
// AND Register-Register-Register (64)
void Assembler::ngrk(Register r1, Register r2, Register r3) {
rrf1_form(NGRK, r1, r2, r3);
@@ -2261,9 +1958,6 @@ void Assembler::oy(Register r1, const MemOperand& opnd) {
rxy_form(OY, r1, opnd.rx(), opnd.rb(), opnd.offset());
}
-// OR Register (32)
-void Assembler::or_z(Register r1, Register r2) { rr_form(OR, r1, r2); }
-
// OR Register-Register-Register (32)
void Assembler::ork(Register r1, Register r2, Register r3) {
rrf1_form(ORK, r1, r2, r3);
@@ -2274,9 +1968,6 @@ void Assembler::og(Register r1, const MemOperand& opnd) {
rxy_form(OG, r1, opnd.rx(), opnd.rb(), opnd.offset());
}
-// OR Register (64)
-void Assembler::ogr(Register r1, Register r2) { rre_form(OGR, r1, r2); }
-
// OR Register-Register-Register (64)
void Assembler::ogrk(Register r1, Register r2, Register r3) {
rrf1_form(OGRK, r1, r2, r3);
@@ -2292,9 +1983,6 @@ void Assembler::xy(Register r1, const MemOperand& opnd) {
rxy_form(XY, r1, opnd.rx(), opnd.rb(), opnd.offset());
}
-// XOR Register (32)
-void Assembler::xr(Register r1, Register r2) { rr_form(XR, r1, r2); }
-
// XOR Register-Register-Register (32)
void Assembler::xrk(Register r1, Register r2, Register r3) {
rrf1_form(XRK, r1, r2, r3);
@@ -2305,9 +1993,6 @@ void Assembler::xg(Register r1, const MemOperand& opnd) {
rxy_form(XG, r1, opnd.rx(), opnd.rb(), opnd.offset());
}
-// XOR Register (64)
-void Assembler::xgr(Register r1, Register r2) { rre_form(XGR, r1, r2); }
-
// XOR Register-Register-Register (64)
void Assembler::xgrk(Register r1, Register r2, Register r3) {
rrf1_form(XGRK, r1, r2, r3);
@@ -2320,19 +2005,6 @@ void Assembler::xc(const MemOperand& opnd1, const MemOperand& opnd2,
opnd2.getBaseRegister(), opnd2.getDisplacement());
}
-// -------------------------------------------
-// Bitwise GPR <-> FPR Conversion Instructions
-// -------------------------------------------
-// Load GR from FPR (64 <- L)
-void Assembler::lgdr(Register r1, DoubleRegister f2) {
- rre_form(LGDR, r1, Register::from_code(f2.code()));
-}
-
-// Load FPR from FR (L <- 64)
-void Assembler::ldgr(DoubleRegister f1, Register r2) {
- rre_form(LDGR, Register::from_code(f1.code()), r2);
-}
-
void Assembler::EnsureSpaceFor(int space_needed) {
if (buffer_space() <= (kGap + space_needed)) {
GrowBuffer(space_needed);
@@ -2547,7 +2219,7 @@ void Assembler::jump(Handle<Code> target, RelocInfo::Mode rmode,
EnsureSpace ensure_space(this);
int32_t target_index = emit_code_target(target, rmode);
- brcl(cond, Operand(target_index), true);
+ brcl(cond, Operand(target_index));
}
// Store (32)
@@ -2621,16 +2293,6 @@ void Assembler::icy(Register r1, const MemOperand& opnd) {
rxy_form(ICY, r1, opnd.rx(), opnd.rb(), opnd.offset());
}
-// Insert Immediate (High)
-void Assembler::iihf(Register r1, const Operand& opnd) {
- ril_form(IIHF, r1, opnd);
-}
-
-// Insert Immediate (low)
-void Assembler::iilf(Register r1, const Operand& opnd) {
- ril_form(IILF, r1, opnd);
-}
-
// Insert Immediate (high high)
void Assembler::iihh(Register r1, const Operand& opnd) {
ri_form(IIHH, r1, opnd);
@@ -2651,164 +2313,46 @@ void Assembler::iill(Register r1, const Operand& opnd) {
ri_form(IILL, r1, opnd);
}
-// Load Immediate 32->64
-void Assembler::lgfi(Register r1, const Operand& opnd) {
- ril_form(LGFI, r1, opnd);
-}
-
// GPR <-> FPR Instructions
// Floating point instructions
//
-// Load zero Register (64)
-void Assembler::lzdr(DoubleRegister r1) {
- rre_form(LZDR, Register::from_code(r1.code()), Register::from_code(0));
-}
-
-// Add Register-Register (LB)
-void Assembler::aebr(DoubleRegister r1, DoubleRegister r2) {
- rre_form(AEBR, Register::from_code(r1.code()),
- Register::from_code(r2.code()));
-}
-
// Add Register-Storage (LB)
void Assembler::adb(DoubleRegister r1, const MemOperand& opnd) {
rxe_form(ADB, Register::from_code(r1.code()), opnd.rx(), opnd.rb(),
opnd.offset());
}
-// Add Register-Register (LB)
-void Assembler::adbr(DoubleRegister r1, DoubleRegister r2) {
- rre_form(ADBR, Register::from_code(r1.code()),
- Register::from_code(r2.code()));
-}
-
-// Compare Register-Register (LB)
-void Assembler::cebr(DoubleRegister r1, DoubleRegister r2) {
- rre_form(CEBR, Register::from_code(r1.code()),
- Register::from_code(r2.code()));
-}
-
// Compare Register-Storage (LB)
void Assembler::cdb(DoubleRegister r1, const MemOperand& opnd) {
rx_form(CD, Register::from_code(r1.code()), opnd.rx(), opnd.rb(),
opnd.offset());
}
-// Compare Register-Register (LB)
-void Assembler::cdbr(DoubleRegister r1, DoubleRegister r2) {
- rre_form(CDBR, Register::from_code(r1.code()),
- Register::from_code(r2.code()));
-}
-
-// Divide Register-Register (LB)
-void Assembler::debr(DoubleRegister r1, DoubleRegister r2) {
- rre_form(DEBR, Register::from_code(r1.code()),
- Register::from_code(r2.code()));
-}
-
// Divide Register-Storage (LB)
void Assembler::ddb(DoubleRegister r1, const MemOperand& opnd) {
rxe_form(DDB, Register::from_code(r1.code()), opnd.rx(), opnd.rb(),
opnd.offset());
}
-// Divide Register-Register (LB)
-void Assembler::ddbr(DoubleRegister r1, DoubleRegister r2) {
- rre_form(DDBR, Register::from_code(r1.code()),
- Register::from_code(r2.code()));
-}
-
-// Multiply Register-Register (LB)
-void Assembler::meebr(DoubleRegister r1, DoubleRegister r2) {
- rre_form(MEEBR, Register::from_code(r1.code()),
- Register::from_code(r2.code()));
-}
-
// Multiply Register-Storage (LB)
void Assembler::mdb(DoubleRegister r1, const MemOperand& opnd) {
rxe_form(MDB, Register::from_code(r1.code()), opnd.rb(), opnd.rx(),
opnd.offset());
}
-// Multiply Register-Register (LB)
-void Assembler::mdbr(DoubleRegister r1, DoubleRegister r2) {
- rre_form(MDBR, Register::from_code(r1.code()),
- Register::from_code(r2.code()));
-}
-
-// Subtract Register-Register (LB)
-void Assembler::sebr(DoubleRegister r1, DoubleRegister r2) {
- rre_form(SEBR, Register::from_code(r1.code()),
- Register::from_code(r2.code()));
-}
-
// Subtract Register-Storage (LB)
void Assembler::sdb(DoubleRegister r1, const MemOperand& opnd) {
rxe_form(SDB, Register::from_code(r1.code()), opnd.rx(), opnd.rb(),
opnd.offset());
}
-// Subtract Register-Register (LB)
-void Assembler::sdbr(DoubleRegister r1, DoubleRegister r2) {
- rre_form(SDBR, Register::from_code(r1.code()),
- Register::from_code(r2.code()));
-}
-
// Square Root (LB)
void Assembler::sqdb(DoubleRegister r1, const MemOperand& opnd) {
rxe_form(SQDB, Register::from_code(r1.code()), opnd.rx(), opnd.rb(),
opnd.offset());
}
-// Square Root Register-Register (LB)
-void Assembler::sqebr(DoubleRegister r1, DoubleRegister r2) {
- rre_form(SQEBR, Register::from_code(r1.code()),
- Register::from_code(r2.code()));
-}
-
-// Square Root Register-Register (LB)
-void Assembler::sqdbr(DoubleRegister r1, DoubleRegister r2) {
- rre_form(SQDBR, Register::from_code(r1.code()),
- Register::from_code(r2.code()));
-}
-
-// Load Rounded (double -> float)
-void Assembler::ledbr(DoubleRegister r1, DoubleRegister r2) {
- rre_form(LEDBR, Register::from_code(r1.code()),
- Register::from_code(r2.code()));
-}
-
-// Load Lengthen (float -> double)
-void Assembler::ldebr(DoubleRegister r1, DoubleRegister r2) {
- rre_form(LDEBR, Register::from_code(r1.code()),
- Register::from_code(r2.code()));
-}
-
-// Load Complement Register-Register (LB)
-void Assembler::lcdbr(DoubleRegister r1, DoubleRegister r2) {
- rre_form(LCDBR, Register::from_code(r1.code()),
- Register::from_code(r2.code()));
-}
-
-// Load Complement Register-Register (LB)
-void Assembler::lcebr(DoubleRegister r1, DoubleRegister r2) {
- rre_form(LCEBR, Register::from_code(r1.code()),
- Register::from_code(r2.code()));
-}
-
-// Load Positive Register-Register (LB)
-void Assembler::lpebr(DoubleRegister r1, DoubleRegister r2) {
- rre_form(LPEBR, Register::from_code(r1.code()),
- Register::from_code(r2.code()));
-}
-
-// Load Positive Register-Register (LB)
-void Assembler::lpdbr(DoubleRegister r1, DoubleRegister r2) {
- rre_form(LPDBR, Register::from_code(r1.code()),
- Register::from_code(r2.code()));
-}
-
// Store Double (64)
void Assembler::std(DoubleRegister r1, const MemOperand& opnd) {
rx_form(STD, r1, opnd.rx(), opnd.rb(), opnd.offset());
@@ -2855,21 +2399,6 @@ void Assembler::ley(DoubleRegister r1, const MemOperand& opnd) {
rxy_form(LEY, r1, opnd.rx(), opnd.rb(), opnd.offset());
}
-// Load Double Register-Register (64)
-void Assembler::ldr(DoubleRegister r1, DoubleRegister r2) {
- rr_form(LDR, r1, r2);
-}
-
-// Load And Test Register-Register (L)
-void Assembler::ltebr(DoubleRegister r1, DoubleRegister r2) {
- rre_form(LTEBR, r1, r2);
-}
-
-// Load And Test Register-Register (L)
-void Assembler::ltdbr(DoubleRegister r1, DoubleRegister r2) {
- rre_form(LTDBR, r1, r2);
-}
-
// Convert to Fixed point (64<-S)
void Assembler::cgebr(Condition m, Register r1, DoubleRegister r2) {
rrfe_form(CGEBR, m, Condition(0), r1, Register::from_code(r2.code()));
@@ -2885,21 +2414,6 @@ void Assembler::cfdbr(Condition m, Register r1, DoubleRegister r2) {
rrfe_form(CFDBR, m, Condition(0), r1, Register::from_code(r2.code()));
}
-// Convert from Fixed point (L<-64)
-void Assembler::cegbr(DoubleRegister r1, Register r2) {
- rre_form(CEGBR, Register::from_code(r1.code()), r2);
-}
-
-// Convert from Fixed point (L<-64)
-void Assembler::cdgbr(DoubleRegister r1, Register r2) {
- rre_form(CDGBR, Register::from_code(r1.code()), r2);
-}
-
-// Convert from Fixed point (L<-32)
-void Assembler::cdfbr(DoubleRegister r1, Register r2) {
- rre_form(CDFBR, Register::from_code(r1.code()), r2);
-}
-
// Convert to Fixed Logical (64<-L)
void Assembler::clgdbr(Condition m3, Condition m4, Register r1,
DoubleRegister r2) {
@@ -2988,20 +2502,6 @@ void Assembler::fidbra(DoubleRegister d1, DoubleRegister d2, FIDBRA_MASK3 m3) {
rrf2_form(FIDBRA << 16 | m3 * B12 | d1.code() * B4 | d2.code());
}
-// Multiply and Add - MADBR R1, R3, R2
-// R1 = R3 * R2 + R1
-void Assembler::madbr(DoubleRegister d1, DoubleRegister d3, DoubleRegister d2) {
- rrd_form(MADBR, Register::from_code(d1.code()),
- Register::from_code(d3.code()), Register::from_code(d2.code()));
-}
-
-// Multiply and Subtract - MSDBR R1, R3, R2
-// R1 = R3 * R2 - R1
-void Assembler::msdbr(DoubleRegister d1, DoubleRegister d3, DoubleRegister d2) {
- rrd_form(MSDBR, Register::from_code(d1.code()),
- Register::from_code(d3.code()), Register::from_code(d2.code()));
-}
-
// end of S390instructions
bool Assembler::IsNop(SixByteInstr instr, int type) {
@@ -3012,6 +2512,21 @@ bool Assembler::IsNop(SixByteInstr instr, int type) {
return ((instr & 0xffff) == 0x1800); // lr r0,r0
}
+// dummy instruction reserved for special use.
+void Assembler::dumy(int r1, int x2, int b2, int d2) {
+#if defined(USE_SIMULATOR)
+ int op = 0xE353;
+ uint64_t code = (static_cast<uint64_t>(op & 0xFF00)) * B32 |
+ (static_cast<uint64_t>(r1) & 0xF) * B36 |
+ (static_cast<uint64_t>(x2) & 0xF) * B32 |
+ (static_cast<uint64_t>(b2) & 0xF) * B28 |
+ (static_cast<uint64_t>(d2 & 0x0FFF)) * B16 |
+ (static_cast<uint64_t>(d2 & 0x0FF000)) >> 4 |
+ (static_cast<uint64_t>(op & 0x00FF));
+ emit6bytes(code);
+#endif
+}
+
void Assembler::GrowBuffer(int needed) {
if (!own_buffer_) FATAL("external code buffer is too small");
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