diff options
Diffstat (limited to 'deps/v8/src/wasm/baseline/mips/liftoff-assembler-mips.h')
| -rw-r--r-- | deps/v8/src/wasm/baseline/mips/liftoff-assembler-mips.h | 421 |
1 files changed, 375 insertions, 46 deletions
diff --git a/deps/v8/src/wasm/baseline/mips/liftoff-assembler-mips.h b/deps/v8/src/wasm/baseline/mips/liftoff-assembler-mips.h index 32215b3df5..8461e0435f 100644 --- a/deps/v8/src/wasm/baseline/mips/liftoff-assembler-mips.h +++ b/deps/v8/src/wasm/baseline/mips/liftoff-assembler-mips.h @@ -59,20 +59,20 @@ inline MemOperand GetInstanceOperand() { return GetStackSlot(kInstanceOffset); } inline void Load(LiftoffAssembler* assm, LiftoffRegister dst, Register base, int32_t offset, ValueType type) { MemOperand src(base, offset); - switch (type) { - case kWasmI32: + switch (type.kind()) { + case ValueType::kI32: assm->lw(dst.gp(), src); break; - case kWasmI64: + case ValueType::kI64: assm->lw(dst.low_gp(), MemOperand(base, offset + liftoff::kLowWordOffset)); assm->lw(dst.high_gp(), MemOperand(base, offset + liftoff::kHighWordOffset)); break; - case kWasmF32: + case ValueType::kF32: assm->lwc1(dst.fp(), src); break; - case kWasmF64: + case ValueType::kF64: assm->Ldc1(dst.fp(), src); break; default: @@ -83,20 +83,20 @@ inline void Load(LiftoffAssembler* assm, LiftoffRegister dst, Register base, inline void Store(LiftoffAssembler* assm, Register base, int32_t offset, LiftoffRegister src, ValueType type) { MemOperand dst(base, offset); - switch (type) { - case kWasmI32: + switch (type.kind()) { + case ValueType::kI32: assm->Usw(src.gp(), dst); break; - case kWasmI64: + case ValueType::kI64: assm->Usw(src.low_gp(), MemOperand(base, offset + liftoff::kLowWordOffset)); assm->Usw(src.high_gp(), MemOperand(base, offset + liftoff::kHighWordOffset)); break; - case kWasmF32: + case ValueType::kF32: assm->Uswc1(src.fp(), dst, t8); break; - case kWasmF64: + case ValueType::kF64: assm->Usdc1(src.fp(), dst, t8); break; default: @@ -105,18 +105,18 @@ inline void Store(LiftoffAssembler* assm, Register base, int32_t offset, } inline void push(LiftoffAssembler* assm, LiftoffRegister reg, ValueType type) { - switch (type) { - case kWasmI32: + switch (type.kind()) { + case ValueType::kI32: assm->push(reg.gp()); break; - case kWasmI64: + case ValueType::kI64: assm->Push(reg.high_gp(), reg.low_gp()); break; - case kWasmF32: + case ValueType::kF32: assm->addiu(sp, sp, -sizeof(float)); assm->swc1(reg.fp(), MemOperand(sp, 0)); break; - case kWasmF64: + case ValueType::kF64: assm->addiu(sp, sp, -sizeof(double)); assm->Sdc1(reg.fp(), MemOperand(sp, 0)); break; @@ -298,17 +298,17 @@ constexpr int LiftoffAssembler::StaticStackFrameSize() { } int LiftoffAssembler::SlotSizeForType(ValueType type) { - switch (type) { - case kWasmS128: - return ValueTypes::ElementSizeInBytes(type); + switch (type.kind()) { + case ValueType::kS128: + return type.element_size_bytes(); default: return kStackSlotSize; } } bool LiftoffAssembler::NeedsAlignment(ValueType type) { - switch (type) { - case kWasmS128: + switch (type.kind()) { + case ValueType::kS128: return true; default: // No alignment because all other types are kStackSlotSize. @@ -318,11 +318,11 @@ bool LiftoffAssembler::NeedsAlignment(ValueType type) { void LiftoffAssembler::LoadConstant(LiftoffRegister reg, WasmValue value, RelocInfo::Mode rmode) { - switch (value.type()) { - case kWasmI32: + switch (value.type().kind()) { + case ValueType::kI32: TurboAssembler::li(reg.gp(), Operand(value.to_i32(), rmode)); break; - case kWasmI64: { + case ValueType::kI64: { DCHECK(RelocInfo::IsNone(rmode)); int32_t low_word = value.to_i64(); int32_t high_word = value.to_i64() >> 32; @@ -330,10 +330,10 @@ void LiftoffAssembler::LoadConstant(LiftoffRegister reg, WasmValue value, TurboAssembler::li(reg.high_gp(), Operand(high_word)); break; } - case kWasmF32: + case ValueType::kF32: TurboAssembler::Move(reg.fp(), value.to_f32_boxed().get_bits()); break; - case kWasmF64: + case ValueType::kF64: TurboAssembler::Move(reg.fp(), value.to_f64_boxed().get_bits()); break; default: @@ -568,6 +568,21 @@ void LiftoffAssembler::AtomicXor(Register dst_addr, Register offset_reg, bailout(kAtomics, "AtomicXor"); } +void LiftoffAssembler::AtomicExchange(Register dst_addr, Register offset_reg, + uint32_t offset_imm, + LiftoffRegister value, StoreType type) { + bailout(kAtomics, "AtomicExchange"); +} + +void LiftoffAssembler::AtomicCompareExchange( + Register dst_addr, Register offset_reg, uint32_t offset_imm, + LiftoffRegister expected, LiftoffRegister new_value, LiftoffRegister result, + StoreType type) { + bailout(kAtomics, "AtomicCompareExchange"); +} + +void LiftoffAssembler::AtomicFence() { sync(); } + void LiftoffAssembler::LoadCallerFrameSlot(LiftoffRegister dst, uint32_t caller_slot_idx, ValueType type) { @@ -597,18 +612,18 @@ void LiftoffAssembler::Move(DoubleRegister dst, DoubleRegister src, void LiftoffAssembler::Spill(int offset, LiftoffRegister reg, ValueType type) { RecordUsedSpillOffset(offset); MemOperand dst = liftoff::GetStackSlot(offset); - switch (type) { - case kWasmI32: + switch (type.kind()) { + case ValueType::kI32: sw(reg.gp(), dst); break; - case kWasmI64: + case ValueType::kI64: sw(reg.low_gp(), liftoff::GetHalfStackSlot(offset, kLowWord)); sw(reg.high_gp(), liftoff::GetHalfStackSlot(offset, kHighWord)); break; - case kWasmF32: + case ValueType::kF32: swc1(reg.fp(), dst); break; - case kWasmF64: + case ValueType::kF64: TurboAssembler::Sdc1(reg.fp(), dst); break; default: @@ -619,14 +634,14 @@ void LiftoffAssembler::Spill(int offset, LiftoffRegister reg, ValueType type) { void LiftoffAssembler::Spill(int offset, WasmValue value) { RecordUsedSpillOffset(offset); MemOperand dst = liftoff::GetStackSlot(offset); - switch (value.type()) { - case kWasmI32: { + switch (value.type().kind()) { + case ValueType::kI32: { LiftoffRegister tmp = GetUnusedRegister(kGpReg); TurboAssembler::li(tmp.gp(), Operand(value.to_i32())); sw(tmp.gp(), dst); break; } - case kWasmI64: { + case ValueType::kI64: { LiftoffRegister tmp = GetUnusedRegister(kGpRegPair); int32_t low_word = value.to_i64(); @@ -647,18 +662,18 @@ void LiftoffAssembler::Spill(int offset, WasmValue value) { void LiftoffAssembler::Fill(LiftoffRegister reg, int offset, ValueType type) { MemOperand src = liftoff::GetStackSlot(offset); - switch (type) { - case kWasmI32: + switch (type.kind()) { + case ValueType::kI32: lw(reg.gp(), src); break; - case kWasmI64: + case ValueType::kI64: lw(reg.low_gp(), liftoff::GetHalfStackSlot(offset, kLowWord)); lw(reg.high_gp(), liftoff::GetHalfStackSlot(offset, kHighWord)); break; - case kWasmF32: + case ValueType::kF32: lwc1(reg.fp(), src); break; - case kWasmF64: + case ValueType::kF64: TurboAssembler::Ldc1(reg.fp(), src); break; default: @@ -1517,12 +1532,328 @@ void LiftoffAssembler::emit_f64_set_cond(Condition cond, Register dst, bind(&cont); } +void LiftoffAssembler::emit_f64x2_splat(LiftoffRegister dst, + LiftoffRegister src) { + // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS + // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming + // 3a4000 support MSA. + bailout(kSimd, "emit_f64x2_splat"); +} + +void LiftoffAssembler::emit_f64x2_extract_lane(LiftoffRegister dst, + LiftoffRegister lhs, + uint8_t imm_lane_idx) { + // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS + // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming + // 3a4000 support MSA. + bailout(kSimd, "emit_f64x2_extract_lane"); +} + +void LiftoffAssembler::emit_f64x2_replace_lane(LiftoffRegister dst, + LiftoffRegister src1, + LiftoffRegister src2, + uint8_t imm_lane_idx) { + // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS + // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming + // 3a4000 support MSA. + bailout(kSimd, "emit_f64x2_replace_lane"); +} + +void LiftoffAssembler::emit_f64x2_add(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS + // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming + // 3a4000 support MSA. + bailout(kSimd, "emit_f64x2_add"); +} + +void LiftoffAssembler::emit_f64x2_sub(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS + // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming + // 3a4000 support MSA. + bailout(kSimd, "emit_f64x2_sub"); +} + +void LiftoffAssembler::emit_f64x2_mul(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS + // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming + // 3a4000 support MSA. + bailout(kSimd, "emit_f64x2_mul"); +} + void LiftoffAssembler::emit_f32x4_splat(LiftoffRegister dst, LiftoffRegister src) { // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming // 3a4000 support MSA. - bailout(kUnsupportedArchitecture, "emit_f32x4_splat"); + bailout(kSimd, "emit_f32x4_splat"); +} + +void LiftoffAssembler::emit_f32x4_extract_lane(LiftoffRegister dst, + LiftoffRegister lhs, + uint8_t imm_lane_idx) { + // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS + // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming + // 3a4000 support MSA. + bailout(kSimd, "emit_f32x4_extract_lane"); +} + +void LiftoffAssembler::emit_f32x4_replace_lane(LiftoffRegister dst, + LiftoffRegister src1, + LiftoffRegister src2, + uint8_t imm_lane_idx) { + // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS + // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming + // 3a4000 support MSA. + bailout(kSimd, "emit_f32x4_replace_lane"); +} + +void LiftoffAssembler::emit_f32x4_add(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS + // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming + // 3a4000 support MSA. + bailout(kSimd, "emit_f32x4_add"); +} + +void LiftoffAssembler::emit_f32x4_sub(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS + // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming + // 3a4000 support MSA. + bailout(kSimd, "emit_f32x4_sub"); +} + +void LiftoffAssembler::emit_f32x4_mul(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS + // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming + // 3a4000 support MSA. + bailout(kSimd, "emit_f32x4_mul"); +} + +void LiftoffAssembler::emit_i64x2_splat(LiftoffRegister dst, + LiftoffRegister src) { + // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS + // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming + // 3a4000 support MSA. + bailout(kSimd, "emit_i64x2_splat"); +} + +void LiftoffAssembler::emit_i64x2_extract_lane(LiftoffRegister dst, + LiftoffRegister lhs, + uint8_t imm_lane_idx) { + // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS + // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming + // 3a4000 support MSA. + bailout(kSimd, "emit_i64x2_extract_lane"); +} + +void LiftoffAssembler::emit_i64x2_replace_lane(LiftoffRegister dst, + LiftoffRegister src1, + LiftoffRegister src2, + uint8_t imm_lane_idx) { + // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS + // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming + // 3a4000 support MSA. + bailout(kSimd, "emit_i64x2_replace_lane"); +} + +void LiftoffAssembler::emit_i64x2_add(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS + // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming + // 3a4000 support MSA. + bailout(kSimd, "emit_i64x2_add"); +} + +void LiftoffAssembler::emit_i64x2_sub(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS + // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming + // 3a4000 support MSA. + bailout(kSimd, "emit_i64x2_sub"); +} + +void LiftoffAssembler::emit_i64x2_mul(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS + // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming + // 3a4000 support MSA. + bailout(kSimd, "emit_i64x2_mul"); +} + +void LiftoffAssembler::emit_i32x4_splat(LiftoffRegister dst, + LiftoffRegister src) { + // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS + // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming + // 3a4000 support MSA. + bailout(kSimd, "emit_i32x4_splat"); +} + +void LiftoffAssembler::emit_i32x4_extract_lane(LiftoffRegister dst, + LiftoffRegister lhs, + uint8_t imm_lane_idx) { + // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS + // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming + // 3a4000 support MSA. + bailout(kSimd, "emit_i32x4_extract_lane"); +} + +void LiftoffAssembler::emit_i32x4_replace_lane(LiftoffRegister dst, + LiftoffRegister src1, + LiftoffRegister src2, + uint8_t imm_lane_idx) { + // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS + // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming + // 3a4000 support MSA. + bailout(kSimd, "emit_i32x4_replace_lane"); +} + +void LiftoffAssembler::emit_i32x4_add(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS + // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming + // 3a4000 support MSA. + bailout(kSimd, "emit_i32x4_add"); +} + +void LiftoffAssembler::emit_i32x4_sub(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS + // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming + // 3a4000 support MSA. + bailout(kSimd, "emit_i32x4_sub"); +} + +void LiftoffAssembler::emit_i32x4_mul(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS + // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming + // 3a4000 support MSA. + bailout(kSimd, "emit_i32x4_mul"); +} + +void LiftoffAssembler::emit_i16x8_splat(LiftoffRegister dst, + LiftoffRegister src) { + // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS + // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming + // 3a4000 support MSA. + bailout(kSimd, "emit_i16x8_splat"); +} + +void LiftoffAssembler::emit_i16x8_extract_lane_u(LiftoffRegister dst, + LiftoffRegister lhs, + uint8_t imm_lane_idx) { + // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS + // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming + // 3a4000 support MSA. + bailout(kSimd, "emit_i16x8_extract_lane_u"); +} + +void LiftoffAssembler::emit_i16x8_extract_lane_s(LiftoffRegister dst, + LiftoffRegister lhs, + uint8_t imm_lane_idx) { + // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS + // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming + // 3a4000 support MSA. + bailout(kSimd, "emit_i16x8_extract_lane_s"); +} + +void LiftoffAssembler::emit_i16x8_replace_lane(LiftoffRegister dst, + LiftoffRegister src1, + LiftoffRegister src2, + uint8_t imm_lane_idx) { + // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS + // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming + // 3a4000 support MSA. + bailout(kSimd, "emit_i16x8_replace_lane"); +} + +void LiftoffAssembler::emit_i16x8_add(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS + // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming + // 3a4000 support MSA. + bailout(kSimd, "emit_i16x8_add"); +} + +void LiftoffAssembler::emit_i16x8_sub(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS + // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming + // 3a4000 support MSA. + bailout(kSimd, "emit_i16x8_sub"); +} + +void LiftoffAssembler::emit_i16x8_mul(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS + // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming + // 3a4000 support MSA. + bailout(kSimd, "emit_i16x8_mul"); +} + +void LiftoffAssembler::emit_i8x16_splat(LiftoffRegister dst, + LiftoffRegister src) { + // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS + // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming + // 3a4000 support MSA. + bailout(kSimd, "emit_i8x16_splat"); +} + +void LiftoffAssembler::emit_i8x16_extract_lane_u(LiftoffRegister dst, + LiftoffRegister lhs, + uint8_t imm_lane_idx) { + // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS + // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming + // 3a4000 support MSA. + bailout(kSimd, "emit_i8x16_extract_lane_u"); +} + +void LiftoffAssembler::emit_i8x16_extract_lane_s(LiftoffRegister dst, + LiftoffRegister lhs, + uint8_t imm_lane_idx) { + // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS + // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming + // 3a4000 support MSA. + bailout(kSimd, "emit_i8x16_extract_lane_s"); +} + +void LiftoffAssembler::emit_i8x16_replace_lane(LiftoffRegister dst, + LiftoffRegister src1, + LiftoffRegister src2, + uint8_t imm_lane_idx) { + // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS + // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming + // 3a4000 support MSA. + bailout(kSimd, "emit_i8x16_replace_lane"); +} + +void LiftoffAssembler::emit_i8x16_add(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS + // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming + // 3a4000 support MSA. + bailout(kSimd, "emit_i8x16_add"); +} + +void LiftoffAssembler::emit_i8x16_sub(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS + // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming + // 3a4000 support MSA. + bailout(kSimd, "emit_i8x16_sub"); +} + +void LiftoffAssembler::emit_i8x16_mul(LiftoffRegister dst, LiftoffRegister lhs, + LiftoffRegister rhs) { + // TODO(mips): Support this on loongson 3a4000. Currently, the main MIPS + // CPU, Loongson 3a3000 does not support MSA(simd128), but the upcoming + // 3a4000 support MSA. + bailout(kSimd, "emit_i8x16_mul"); } void LiftoffAssembler::StackCheck(Label* ool_code, Register limit_address) { @@ -1595,7 +1926,7 @@ void LiftoffAssembler::DropStackSlotsAndRet(uint32_t num_stack_slots) { TurboAssembler::DropAndRet(static_cast<int>(num_stack_slots)); } -void LiftoffAssembler::CallC(wasm::FunctionSig* sig, +void LiftoffAssembler::CallC(const wasm::FunctionSig* sig, const LiftoffRegister* args, const LiftoffRegister* rets, ValueType out_argument_type, int stack_bytes, @@ -1605,7 +1936,7 @@ void LiftoffAssembler::CallC(wasm::FunctionSig* sig, int arg_bytes = 0; for (ValueType param_type : sig->parameters()) { liftoff::Store(this, sp, arg_bytes, *args++, param_type); - arg_bytes += ValueTypes::MemSize(param_type); + arg_bytes += param_type.element_size_bytes(); } DCHECK_LE(arg_bytes, stack_bytes); @@ -1642,7 +1973,7 @@ void LiftoffAssembler::CallNativeWasmCode(Address addr) { Call(addr, RelocInfo::WASM_CALL); } -void LiftoffAssembler::CallIndirect(wasm::FunctionSig* sig, +void LiftoffAssembler::CallIndirect(const wasm::FunctionSig* sig, compiler::CallDescriptor* call_descriptor, Register target) { if (target == no_reg) { @@ -1668,14 +1999,12 @@ void LiftoffAssembler::DeallocateStackSlot(uint32_t size) { addiu(sp, sp, size); } -void LiftoffAssembler::DebugBreak() { stop(); } - void LiftoffStackSlots::Construct() { for (auto& slot : slots_) { const LiftoffAssembler::VarState& src = slot.src_; switch (src.loc()) { case LiftoffAssembler::VarState::kStack: { - if (src.type() == kWasmF64) { + if (src.type().kind() == ValueType::kF64) { DCHECK_EQ(kLowWord, slot.half_); asm_->lw(kScratchReg, liftoff::GetHalfStackSlot(slot.src_offset_, kHighWord)); @@ -1687,7 +2016,7 @@ void LiftoffStackSlots::Construct() { break; } case LiftoffAssembler::VarState::kRegister: - if (src.type() == kWasmI64) { + if (src.type().kind() == ValueType::kI64) { liftoff::push( asm_, slot.half_ == kLowWord ? src.reg().low() : src.reg().high(), kWasmI32); |