diff options
| author | Alexandre Courbot <acourbot@nvidia.com> | 2016-06-01 17:39:29 +0900 |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2016-07-14 11:51:54 +1000 |
| commit | f23846776efe50bdbf49d48930ee1dab9c70600a (patch) | |
| tree | 5b18d01909c5df231ebc7071b67e8e14c6446f36 /lib/include/nvif | |
| parent | 2464908ccf0d06fb44fa46afcc72a54242900cd8 (diff) | |
| download | nouveau-f23846776efe50bdbf49d48930ee1dab9c70600a.tar.gz | |
clk/gm20b: add glitchless and DFS support
This patch adds support for advanced features supported by the
Noise-Aware PLL of Maxwell. Glitchless switch allows the PL field to be
updated without disabling the PLL first if the SYNC_MODE bit of the CFG
register is set.
More significantly, DFS allows the PLL to monitor the actual input
voltage and to dynamically lower the output frequency accordingly. This
allows the clock to be more tolerant of lower voltages.
These improvements are only supported for Tegra speedos >= 1.
Also add the voltage table that is suitable for GM20B's NAPLL. This
change needs to be done atomically for the right voltages to be used by
the clock driver.
v2. Fix build on non-Tegra platforms
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'lib/include/nvif')
| -rw-r--r-- | lib/include/nvif/os.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/lib/include/nvif/os.h b/lib/include/nvif/os.h index 4cd65e3cf..c265ab446 100644 --- a/lib/include/nvif/os.h +++ b/lib/include/nvif/os.h @@ -136,6 +136,12 @@ typedef dma_addr_t resource_size_t; #define IS_ENABLED_CONFIG_IOMMU_API 0 #endif +#if defined(CONFIG_ARCH_TEGRA) +#define IS_ENABLED_CONFIG_ARCH_TEGRA 1 +#else +#define IS_ENABLED_CONFIG_ARCH_TEGRA 0 +#endif + #define IS_ENABLED(x) IS_ENABLED_##x static inline bool @@ -229,6 +235,7 @@ hweight32(u32 v) { return i; } +#define BITS_PER_BYTE 8 #define BITS_PER_LONG (sizeof(unsigned long) * 8) #define BITS_TO_LONGS(b) DIV_ROUND_UP((b), BITS_PER_LONG) #define DECLARE_BITMAP(n,b) unsigned long n[BITS_TO_LONGS(b)] @@ -1553,6 +1560,13 @@ tegra_powergate_remove_clamping(int id) return -ENOSYS; } +static inline int +tegra_fuse_readl(unsigned long offset, u32 *value) +{ + *value = 0; + return -ENOSYS; +} + /****************************************************************************** * endianness (cont'd) *****************************************************************************/ |