diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2013-01-31 19:49:33 -0500 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2013-02-20 15:55:25 +1000 |
commit | 673ad33464afdbe5945aa084a97def25ea8e1946 (patch) | |
tree | 68127c558a7f1cfd772e2098edf5c295619ea8ba /nvkm/engine | |
parent | 0dc5c375441dacd2c4fd1125436bbf3947ab420e (diff) | |
download | nouveau-673ad33464afdbe5945aa084a97def25ea8e1946.tar.gz |
fifo/nvc0: improve interrupt handler somewhat
Logs extra info for interrupts that have a sub-status register, and
handles the "special" ack from INTR bit 31.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'nvkm/engine')
-rw-r--r-- | nvkm/engine/fifo/nvc0.c | 36 |
1 files changed, 33 insertions, 3 deletions
diff --git a/nvkm/engine/fifo/nvc0.c b/nvkm/engine/fifo/nvc0.c index 1580aae7e..2a9919bbf 100644 --- a/nvkm/engine/fifo/nvc0.c +++ b/nvkm/engine/fifo/nvc0.c @@ -517,12 +517,34 @@ nvc0_fifo_intr(struct nouveau_subdev *subdev) u32 mask = nv_rd32(priv, 0x002140); u32 stat = nv_rd32(priv, 0x002100) & mask; + if (stat & 0x00000001) { + u32 intr = nv_rd32(priv, 0x00252c); + nv_warn(priv, "INTR 0x00000001: 0x%08x\n", intr); + nv_wr32(priv, 0x002100, 0x00000001); + stat &= ~0x00000001; + } + if (stat & 0x00000100) { - nv_warn(priv, "unknown status 0x00000100\n"); + u32 intr = nv_rd32(priv, 0x00254c); + nv_warn(priv, "INTR 0x00000100: 0x%08x\n", intr); nv_wr32(priv, 0x002100, 0x00000100); stat &= ~0x00000100; } + if (stat & 0x00010000) { + u32 intr = nv_rd32(priv, 0x00256c); + nv_warn(priv, "INTR 0x00010000: 0x%08x\n", intr); + nv_wr32(priv, 0x002100, 0x00010000); + stat &= ~0x00010000; + } + + if (stat & 0x01000000) { + u32 intr = nv_rd32(priv, 0x00258c); + nv_warn(priv, "INTR 0x01000000: 0x%08x\n", intr); + nv_wr32(priv, 0x002100, 0x01000000); + stat &= ~0x01000000; + } + if (stat & 0x10000000) { u32 units = nv_rd32(priv, 0x00259c); u32 u = units; @@ -552,11 +574,19 @@ nvc0_fifo_intr(struct nouveau_subdev *subdev) } if (stat & 0x40000000) { - nv_warn(priv, "unknown status 0x40000000\n"); - nv_mask(priv, 0x002a00, 0x00000000, 0x00000000); + u32 intr0 = nv_rd32(priv, 0x0025a4); + u32 intr1 = nv_mask(priv, 0x002a00, 0x00000000, 0x00000); + nv_debug(priv, "INTR 0x40000000: 0x%08x 0x%08x\n", + intr0, intr1); stat &= ~0x40000000; } + if (stat & 0x80000000) { + u32 intr = nv_mask(priv, 0x0025a8, 0x00000000, 0x00000000); + nv_warn(priv, "INTR 0x80000000: 0x%08x\n", intr); + stat &= ~0x80000000; + } + if (stat) { nv_fatal(priv, "unhandled status 0x%08x\n", stat); nv_wr32(priv, 0x002100, stat); |