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authorWan-Teh Chang <wtc@google.com>2014-04-27 20:04:51 -0700
committerWan-Teh Chang <wtc@google.com>2014-04-27 20:04:51 -0700
commit9ecea72ce67de8f630142dcaeab51f01426d55ea (patch)
tree73209d80b743051d0fc4de4f4528c32b7f05b71f
parent0788eeb6ef2ce0f651e4849a58e58003072c0fbd (diff)
downloadnss-hg-9ecea72ce67de8f630142dcaeab51f01426d55ea.tar.gz
Bug 979703: Avoid _xgetbv() for 32-bit x86 builds so that we can use theNSS_3_16_1_BETA3
Intel AES assembly code with VC 2010 RTM. r=cviecco.
-rw-r--r--lib/freebl/Makefile6
-rw-r--r--lib/freebl/rijndael.c11
2 files changed, 14 insertions, 3 deletions
diff --git a/lib/freebl/Makefile b/lib/freebl/Makefile
index dbf386200..2a51501bb 100644
--- a/lib/freebl/Makefile
+++ b/lib/freebl/Makefile
@@ -135,9 +135,9 @@ else
ifdef BUILD_OPT
OPTIMIZER += -Ox # maximum optimization for freebl
endif
- # The Intel AES assembly code requires Visual C++ 2010 (10.0). The _xgetbv
- # compiler intrinsic function requires Visual C++ 2010 (10.0) SP1.
- ifeq ($(_MSC_VER_GE_10SP1),1)
+ # The Intel AES assembly code requires Visual C++ 2010.
+ # if $(_MSC_VER) >= 1600 (Visual C++ 2010)
+ ifeq ($(firstword $(sort $(_MSC_VER) 1600)),1600)
DEFINES += -DUSE_HW_AES -DINTEL_GCM
ASFILES += intel-aes-x86-masm.asm intel-gcm-x86-masm.asm
EXTRA_SRCS += intel-gcm-wrap.c
diff --git a/lib/freebl/rijndael.c b/lib/freebl/rijndael.c
index 67057c701..4e4be79fd 100644
--- a/lib/freebl/rijndael.c
+++ b/lib/freebl/rijndael.c
@@ -972,13 +972,24 @@ AESContext * AES_AllocateContext(void)
/*
* Adapted from the example code in "How to detect New Instruction support in
* the 4th generation Intel Core processor family" by Max Locktyukhin.
+ *
+ * XGETBV:
+ * Reads an extended control register (XCR) specified by ECX into EDX:EAX.
*/
static PRBool
check_xcr0_ymm()
{
PRUint32 xcr0;
#if defined(_MSC_VER)
+#if defined(_M_IX86)
+ __asm {
+ mov ecx, 0
+ xgetbv
+ mov xcr0, eax
+ }
+#else
xcr0 = (PRUint32)_xgetbv(0); /* Requires VS2010 SP1 or later. */
+#endif
#else
__asm__ ("xgetbv" : "=a" (xcr0) : "c" (0) : "%edx");
#endif