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| author | Franziskus Kiefer <franziskuskiefer@gmail.com> | 2019-12-18 18:03:47 +0000 |
|---|---|---|
| committer | Franziskus Kiefer <franziskuskiefer@gmail.com> | 2019-12-18 18:03:47 +0000 |
| commit | 68b1199d47ed97fc3f9e6c7802db1ebcf1b061dc (patch) | |
| tree | e52cb250fd26ec986d1c57ebd128decf0aeea28d /lib/freebl/blinit.c | |
| parent | c14ffa8ce439d8c9c40e97639ae895a0de5a7b65 (diff) | |
| download | nss-hg-68b1199d47ed97fc3f9e6c7802db1ebcf1b061dc.tar.gz | |
Bug 1574643 - NSS changes for haclv2 r=jcj,kjacobs
This patch contains the changes in NSS, necessary to pick up HACL*v2 in D55413. It has a couple of TODOs:
* The chacha20 saw verification fails for some reason; it's disabled pending Bug 1604130.
* The hacl task on CI requires Bug 1593647 to get fixed.
Depends on D55413.
Differential Revision: https://phabricator.services.mozilla.com/D55414
Diffstat (limited to 'lib/freebl/blinit.c')
| -rw-r--r-- | lib/freebl/blinit.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/lib/freebl/blinit.c b/lib/freebl/blinit.c index 959109b60..3bdccd8a5 100644 --- a/lib/freebl/blinit.c +++ b/lib/freebl/blinit.c @@ -24,6 +24,8 @@ static PRBool aesni_support_ = PR_FALSE; static PRBool clmul_support_ = PR_FALSE; static PRBool avx_support_ = PR_FALSE; static PRBool ssse3_support_ = PR_FALSE; +static PRBool sse4_1_support_ = PR_FALSE; +static PRBool sse4_2_support_ = PR_FALSE; static PRBool arm_neon_support_ = PR_FALSE; static PRBool arm_aes_support_ = PR_FALSE; static PRBool arm_sha1_support_ = PR_FALSE; @@ -70,6 +72,8 @@ check_xcr0_ymm() #define ECX_OSXSAVE (1 << 27) #define ECX_AVX (1 << 28) #define ECX_SSSE3 (1 << 9) +#define ECX_SSE4_1 (1 << 19) +#define ECX_SSE4_2 (1 << 20) #define AVX_BITS (ECX_XSAVE | ECX_OSXSAVE | ECX_AVX) void @@ -80,6 +84,8 @@ CheckX86CPUSupport() char *disable_pclmul = PR_GetEnvSecure("NSS_DISABLE_PCLMUL"); char *disable_avx = PR_GetEnvSecure("NSS_DISABLE_AVX"); char *disable_ssse3 = PR_GetEnvSecure("NSS_DISABLE_SSSE3"); + char *disable_sse4_1 = PR_GetEnvSecure("NSS_DISABLE_SSE4_1"); + char *disable_sse4_2 = PR_GetEnvSecure("NSS_DISABLE_SSE4_2"); freebl_cpuid(1, &eax, &ebx, &ecx, &edx); aesni_support_ = (PRBool)((ecx & ECX_AESNI) != 0 && disable_hw_aes == NULL); clmul_support_ = (PRBool)((ecx & ECX_CLMUL) != 0 && disable_pclmul == NULL); @@ -89,6 +95,10 @@ CheckX86CPUSupport() disable_avx == NULL; ssse3_support_ = (PRBool)((ecx & ECX_SSSE3) != 0 && disable_ssse3 == NULL); + sse4_1_support_ = (PRBool)((ecx & ECX_SSE4_1) != 0 && + disable_sse4_1 == NULL); + sse4_2_support_ = (PRBool)((ecx & ECX_SSE4_2) != 0 && + disable_sse4_2 == NULL); } #endif /* NSS_X86_OR_X64 */ @@ -325,6 +335,16 @@ ssse3_support() return ssse3_support_; } PRBool +sse4_1_support() +{ + return sse4_1_support_; +} +PRBool +sse4_2_support() +{ + return sse4_2_support_; +} +PRBool arm_neon_support() { return arm_neon_support_; |