Add the Tamonten™ NG Evaluation Carrier board

Add the build script to create bootable image for the Tamonten™ NG
Evaluation Carrier board using the Tamonten™ NG COM module.

Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
Signed-off-by: Stephen Warren <swarren@nvidia.com>

3 files changed, 289 insertions, 0 deletions

diff --git a/tegra30/avionic-design/tamonten-ng/TamontenNG_Nanya_1GB_NT5CC256M16CP-DI_750MHz_emmc.bct.cfg b/tegra30/avionic-design/tamonten-ng/TamontenNG_Nanya_1GB_NT5CC256M16CP-DI_750MHz_emmc.bct.cfg
new file mode 100644
index 0000000..277a433
--- /dev/null
+++ b/tegra30/avionic-design/tamonten-ng/TamontenNG_Nanya_1GB_NT5CC256M16CP-DI_750MHz_emmc.bct.cfg
@@ -0,0 +1,240 @@
+# Copyright (C) 2013 Avionic Design GmbH
+#
+# This software is provided 'as-is', without any express or implied
+# warranty. In no event will the authors be held liable for any damages
+# arising from the use of this software.
+#
+# Permission is granted to anyone to use this software for any purpose,
+# including commercial applications, and to alter it and redistribute it
+# freely, subject to the following restrictions:
+#
+# 1. The origin of this software must not be misrepresented; you must not
+#    claim that you wrote the original software. If you use this software
+#    in a product, an acknowledgment in the product documentation would be
+#    appreciated but is not required.
+# 2. Altered source versions must be plainly marked as such, and must not be
+#    misrepresented as being the original software.
+# 3. This notice may not be removed or altered from any source distribution.
+
+Version       = 0x00030001;
+BlockSize     = 0x00004000;
+PageSize      = 0x00000200;
+PartitionSize = 0x02000000;
+OdmData       = 0x400c0000;
+
+DevType[0] = NvBootDevType_Sdmmc;
+DeviceParam[0].SdmmcParams.ClockDivider           = 0x00000009;
+DeviceParam[0].SdmmcParams.DataWidth              = NvBootSdmmcDataWidth_8Bit;
+DeviceParam[0].SdmmcParams.MaxPowerClassSupported = 0x00000000;
+DeviceParam[0].SdmmcParams.SdController           = 0x00000000;
+
+DevType[1] = NvBootDevType_Sdmmc;
+DeviceParam[1].SdmmcParams.ClockDivider           = 0x00000009;
+DeviceParam[1].SdmmcParams.DataWidth              = NvBootSdmmcDataWidth_8Bit;
+DeviceParam[1].SdmmcParams.MaxPowerClassSupported = 0x00000000;
+DeviceParam[1].SdmmcParams.SdController           = 0x00000000;
+
+DevType[2] = NvBootDevType_Sdmmc;
+DeviceParam[2].SdmmcParams.ClockDivider           = 0x00000009;
+DeviceParam[2].SdmmcParams.DataWidth              = NvBootSdmmcDataWidth_8Bit;
+DeviceParam[2].SdmmcParams.MaxPowerClassSupported = 0x00000000;
+DeviceParam[2].SdmmcParams.SdController           = 0x00000000;
+
+DevType[3] = NvBootDevType_Sdmmc;
+DeviceParam[3].SdmmcParams.ClockDivider           = 0x00000009;
+DeviceParam[3].SdmmcParams.DataWidth              = NvBootSdmmcDataWidth_8Bit;
+DeviceParam[3].SdmmcParams.MaxPowerClassSupported = 0x00000000;
+DeviceParam[3].SdmmcParams.SdController           = 0x00000000;
+
+SDRAM[0].MemoryType                               = NvBootMemoryType_Ddr3;
+SDRAM[0].PllMChargePumpSetupControl               = 0x00000008;
+SDRAM[0].PllMLoopFilterSetupControl               = 0x00000000;
+SDRAM[0].PllMInputDivider                         = 0x0000000c;
+SDRAM[0].PllMFeedbackDivider                      = 0x000002ee;
+SDRAM[0].PllMPostDivider                          = 0x00000000;
+SDRAM[0].PllMStableTime                           = 0x0000012c;
+SDRAM[0].EmcClockDivider                          = 0x00000000;
+SDRAM[0].EmcClockSource                           = 0x00000000;
+SDRAM[0].EmcClockUsePllMUD                        = 0x00000001;
+SDRAM[0].EmcAutoCalInterval                       = 0x001fffff;
+SDRAM[0].EmcAutoCalConfig                         = 0xa0f10000;
+SDRAM[0].EmcAutoCalWait                           = 0x00000064;
+SDRAM[0].EmcAdrCfg                                = 0x00000000;
+SDRAM[0].EmcPinProgramWait                        = 0x00000001;
+SDRAM[0].EmcPinExtraWait                          = 0x00000000;
+SDRAM[0].EmcTimingControlWait                     = 0x00000000;
+SDRAM[0].EmcRc                                    = 0x00000023;
+SDRAM[0].EmcRfc                                   = 0x00000094;
+SDRAM[0].EmcRas                                   = 0x00000019;
+SDRAM[0].EmcRp                                    = 0x00000009;
+SDRAM[0].EmcR2w                                   = 0x00000005;
+SDRAM[0].EmcW2r                                   = 0x0000000d;
+SDRAM[0].EmcR2p                                   = 0x00000004;
+SDRAM[0].EmcW2p                                   = 0x00000013;
+SDRAM[0].EmcRdRcd                                 = 0x00000009;
+SDRAM[0].EmcWrRcd                                 = 0x00000009;
+SDRAM[0].EmcRrd                                   = 0x00000004;
+SDRAM[0].EmcRext                                  = 0x00000001;
+SDRAM[0].EmcWext                                  = 0x00000000;
+SDRAM[0].EmcWdv                                   = 0x00000007;
+SDRAM[0].EmcQUse                                  = 0x0000000c;
+SDRAM[0].EmcQRst                                  = 0x00000009;
+SDRAM[0].EmcQSafe                                 = 0x0000000a;
+SDRAM[0].EmcRdv                                   = 0x00000012;
+SDRAM[0].EmcCtt                                   = 0x00000000;
+SDRAM[0].EmcCttDuration                           = 0x00000000;
+SDRAM[0].EmcRefresh                               = 0x0000169a;
+SDRAM[0].EmcBurstRefreshNum                       = 0x00000000;
+SDRAM[0].EmcPreRefreshReqCnt                      = 0x000005a6;
+SDRAM[0].EmcPdEx2Wr                               = 0x00000003;
+SDRAM[0].EmcPdEx2Rd                               = 0x00000010;
+SDRAM[0].EmcPChg2Pden                             = 0x00000001;
+SDRAM[0].EmcAct2Pden                              = 0x00000000;
+SDRAM[0].EmcAr2Pden                               = 0x0000000e;
+SDRAM[0].EmcRw2Pden                               = 0x00000018;
+SDRAM[0].EmcTxsr                                  = 0x0000009e;
+SDRAM[0].EmcTxsrDll                               = 0x00000200;
+SDRAM[0].EmcTcke                                  = 0x00000005;
+SDRAM[0].EmcTfaw                                  = 0x0000001e;
+SDRAM[0].EmcTrpab                                 = 0x00000000;
+SDRAM[0].EmcTClkStable                            = 0x00000007;
+SDRAM[0].EmcTClkStop                              = 0x00000008;
+SDRAM[0].EmcTRefBw                                = 0x000016da;
+SDRAM[0].EmcQUseExtra                             = 0x00000000;
+SDRAM[0].EmcFbioCfg5                              = 0x00005088;
+SDRAM[0].EmcFbioCfg6                              = 0x00000004;
+SDRAM[0].EmcFbioSpare                             = 0xd8000000;
+SDRAM[0].EmcCfgRsv                                = 0xff00ff49;
+SDRAM[0].EmcMrs                                   = 0x80000d71;
+SDRAM[0].EmcEmrs                                  = 0x80100002;
+SDRAM[0].EmcMrw1                                  = 0x00000000;
+SDRAM[0].EmcMrw2                                  = 0x00000000;
+SDRAM[0].EmcMrw3                                  = 0x00000000;
+SDRAM[0].EmcMrwExtra                              = 0x00000000;
+SDRAM[0].EmcWarmBootMrw1                          = 0x00000000;
+SDRAM[0].EmcWarmBootMrw2                          = 0x00000000;
+SDRAM[0].EmcWarmBootMrw3                          = 0x00000000;
+SDRAM[0].EmcWarmBootMrwExtra                      = 0x00000000;
+SDRAM[0].EmcWarmBootExtraModeRegWriteEnable       = 0x00000000;
+SDRAM[0].EmcExtraModeRegWriteEnable               = 0x00000000;
+SDRAM[0].EmcMrwResetCommand                       = 0x00000000;
+SDRAM[0].EmcMrwResetNInitWait                     = 0x00000000;
+SDRAM[0].EmcMrsWaitCnt                            = 0x012a000c;
+SDRAM[0].EmcCfg                                   = 0x23e00000;
+SDRAM[0].EmcCfg2                                  = 0x000c0099;
+SDRAM[0].EmcDbg                                   = 0x01000400;
+SDRAM[0].EmcCmdQ                                  = 0x10004408;
+SDRAM[0].EmcMc2EmcQ                               = 0x06000404;
+SDRAM[0].EmcDynSelfRefControl                     = 0x80002d93;
+SDRAM[0].AhbArbitrationXbarCtrlMemInitDone        = 0x00000001;
+SDRAM[0].EmcCfgDigDll                             = 0xf0080191;
+SDRAM[0].EmcCfgDigDllPeriod                       = 0x00008000;
+SDRAM[0].EmcDevSelect                             = 0x00000002;
+SDRAM[0].EmcSelDpdCtrl                            = 0x0004032c;
+SDRAM[0].EmcDllXformDqs0                          = 0x00000008;
+SDRAM[0].EmcDllXformDqs1                          = 0x00000008;
+SDRAM[0].EmcDllXformDqs2                          = 0x00000008;
+SDRAM[0].EmcDllXformDqs3                          = 0x00000008;
+SDRAM[0].EmcDllXformDqs4                          = 0x00000008;
+SDRAM[0].EmcDllXformDqs5                          = 0x00000008;
+SDRAM[0].EmcDllXformDqs6                          = 0x00000008;
+SDRAM[0].EmcDllXformDqs7                          = 0x00000008;
+SDRAM[0].EmcDllXformQUse0                         = 0x00000000;
+SDRAM[0].EmcDllXformQUse1                         = 0x00000000;
+SDRAM[0].EmcDllXformQUse2                         = 0x00000000;
+SDRAM[0].EmcDllXformQUse3                         = 0x00000000;
+SDRAM[0].EmcDllXformQUse4                         = 0x00000000;
+SDRAM[0].EmcDllXformQUse5                         = 0x00000000;
+SDRAM[0].EmcDllXformQUse6                         = 0x00000000;
+SDRAM[0].EmcDllXformQUse7                         = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs0                         = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs1                         = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs2                         = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs3                         = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs4                         = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs5                         = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs6                         = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs7                         = 0x00000000;
+SDRAM[0].EmcDllXformDq0                           = 0x0000000c;
+SDRAM[0].EmcDllXformDq1                           = 0x0000000c;
+SDRAM[0].EmcDllXformDq2                           = 0x0000000c;
+SDRAM[0].EmcDllXformDq3                           = 0x0000000c;
+SDRAM[0].WarmBootWait                             = 0x00000002;
+SDRAM[0].EmcCttTermCtrl                           = 0x00000802;
+SDRAM[0].EmcOdtWrite                              = 0x00000000;
+SDRAM[0].EmcOdtRead                               = 0x00000000;
+SDRAM[0].EmcZcalInterval                          = 0x00020000;
+SDRAM[0].EmcZcalWaitCnt                           = 0x00000040;
+SDRAM[0].EmcZcalMrwCmd                            = 0x80000000;
+SDRAM[0].EmcMrsResetDll                           = 0x00000000;
+SDRAM[0].EmcZcalInitDev0                          = 0x80000011;
+SDRAM[0].EmcZcalInitDev1                          = 0x00000000;
+SDRAM[0].EmcZcalInitWait                          = 0x00000001;
+SDRAM[0].EmcZcalColdBootEnable                    = 0x00000001;
+SDRAM[0].EmcZcalWarmBootEnable                    = 0x00000001;
+SDRAM[0].EmcMrwLpddr2ZcalWarmBoot                 = 0x000a00ab;
+SDRAM[0].EmcZqCalDdr3WarmBoot                     = 0x00000011;
+SDRAM[0].EmcZcalWarmBootWait                      = 0x00000001;
+SDRAM[0].EmcMrsWarmBootEnable                     = 0x00000001;
+SDRAM[0].EmcMrsResetDllWait                       = 0x00000000;
+SDRAM[0].EmcEmrsEmr2                              = 0x80200018;
+SDRAM[0].EmcEmrsEmr3                              = 0x80300000;
+SDRAM[0].EmcMrsExtra                              = 0x80000d71;
+SDRAM[0].EmcWarmBootMrs                           = 0x80100002;
+SDRAM[0].EmcWarmBootEmrs                          = 0x80000d71;
+SDRAM[0].EmcWarmBootEmr2                          = 0x80200018;
+SDRAM[0].EmcWarmBootEmr3                          = 0x80300000;
+SDRAM[0].EmcWarmBootMrsExtra                      = 0x80100002;
+SDRAM[0].EmcEmrsDdr2DllEnable                     = 0x00000000;
+SDRAM[0].EmcMrsDdr2DllReset                       = 0x00000000;
+SDRAM[0].EmcEmrsDdr2OcdCalib                      = 0x00000000;
+SDRAM[0].EmcDdr2Wait                              = 0x00000000;
+SDRAM[0].EmcClkenOverride                         = 0x00000000;
+SDRAM[0].EmcExtraRefreshNum                       = 0x00000002;
+SDRAM[0].EmcClkenOverrideAllWarmBoot              = 0x00000000;
+SDRAM[0].McClkenOverrideAllWarmBoot               = 0x00000000;
+SDRAM[0].EmcCfgDigDllPeriodWarmBoot               = 0x00000003;
+SDRAM[0].PmcVddpSel                               = 0x00000002;
+SDRAM[0].PmcDdrPwr                                = 0x00000003;
+SDRAM[0].PmcDdrCfg                                = 0x00000002;
+SDRAM[0].PmcIoDpdReq                              = 0x80800000;
+SDRAM[0].PmcENoVttGen                             = 0x00000000;
+SDRAM[0].PmcNoIoPower                             = 0x00000000;
+SDRAM[0].EmcXm2CmdPadCtrl                         = 0x000002a0;
+SDRAM[0].EmcXm2CmdPadCtrl2                        = 0x770c0000;
+SDRAM[0].EmcXm2DqsPadCtrl                         = 0x770c1414;
+SDRAM[0].EmcXm2DqsPadCtrl2                        = 0x0800013d;
+SDRAM[0].EmcXm2DqsPadCtrl3                        = 0x08000021;
+SDRAM[0].EmcXm2DqPadCtrl                          = 0x770c2990;
+SDRAM[0].EmcXm2DqPadCtrl2                         = 0x22220000;
+SDRAM[0].EmcXm2ClkPadCtrl                         = 0x77fff884;
+SDRAM[0].EmcXm2CompPadCtrl                        = 0x01f1f501;
+SDRAM[0].EmcXm2VttGenPadCtrl                      = 0x07077404;
+SDRAM[0].EmcXm2VttGenPadCtrl2                     = 0x54000000;
+SDRAM[0].EmcXm2QUsePadCtrl                        = 0x080001e8;
+SDRAM[0].McEmemAdrCfg                             = 0x00000000;
+SDRAM[0].McEmemAdrCfgDev0                         = 0x00080303;
+SDRAM[0].McEmemAdrCfgDev1                         = 0x00080303;
+SDRAM[0].McEmemCfg                                = 0x00000400;
+SDRAM[0].McEmemArbCfg                             = 0x0000000b;
+SDRAM[0].McEmemArbOutstandingReq                  = 0x80000087;
+SDRAM[0].McEmemArbTimingRcd                       = 0x00000004;
+SDRAM[0].McEmemArbTimingRp                        = 0x00000005;
+SDRAM[0].McEmemArbTimingRc                        = 0x00000012;
+SDRAM[0].McEmemArbTimingRas                       = 0x0000000c;
+SDRAM[0].McEmemArbTimingFaw                       = 0x0000000e;
+SDRAM[0].McEmemArbTimingRrd                       = 0x00000002;
+SDRAM[0].McEmemArbTimingRap2Pre                   = 0x00000003;
+SDRAM[0].McEmemArbTimingWap2Pre                   = 0x0000000c;
+SDRAM[0].McEmemArbTimingR2R                       = 0x00000002;
+SDRAM[0].McEmemArbTimingW2W                       = 0x00000002;
+SDRAM[0].McEmemArbTimingR2W                       = 0x00000004;
+SDRAM[0].McEmemArbTimingW2R                       = 0x00000008;
+SDRAM[0].McEmemArbDaTurns                         = 0x08040202;
+SDRAM[0].McEmemArbDaCovers                        = 0x00160d12;
+SDRAM[0].McEmemArbMisc0                           = 0x710c2213;
+SDRAM[0].McEmemArbMisc1                           = 0x78000000;
+SDRAM[0].McEmemArbRing1Throttle                   = 0x001f0000;
+SDRAM[0].McEmemArbOverride                        = 0x00000080;
+SDRAM[0].McEmemArbRsv                             = 0xff00ff00;
+SDRAM[0].McClkenOverride                          = 0x00000000;
diff --git a/tegra30/avionic-design/tamonten-ng/tegra30.img.cfg b/tegra30/avionic-design/tamonten-ng/tegra30.img.cfg
new file mode 100644
index 0000000..c137519
--- /dev/null
+++ b/tegra30/avionic-design/tamonten-ng/tegra30.img.cfg
@@ -0,0 +1,22 @@
+# Copyright (C) 2013 Avionic Design GmbH
+#
+# This software is provided 'as-is', without any express or implied
+# warranty. In no event will the authors be held liable for any damages
+# arising from the use of this software.
+#
+# Permission is granted to anyone to use this software for any purpose,
+# including commercial applications, and to alter it and redistribute it
+# freely, subject to the following restrictions:
+#
+# 1. The origin of this software must not be misrepresented; you must not
+#    claim that you wrote the original software. If you use this software
+#    in a product, an acknowledgment in the product documentation would be
+#    appreciated but is not required.
+# 2. Altered source versions must be plainly marked as such, and must not be
+#    misrepresented as being the original software.
+# 3. This notice may not be removed or altered from any source distribution.
+
+Version       = 0x00020001;
+Bctcopy       = 1;
+Bctfile       = TamontenNG_Nanya_1GB_NT5CC256M16CP-DI_750MHz_emmc.bct;
+BootLoader    = u-boot.bin,0x80108000,0x80108000,Complete;
diff --git a/tegra30/avionic-design/tec-ng/build.sh b/tegra30/avionic-design/tec-ng/build.sh
new file mode 100755
index 0000000..f522c12
--- /dev/null
+++ b/tegra30/avionic-design/tec-ng/build.sh
@@ -0,0 +1,27 @@
+#!/bin/sh
+
+# Copyright (C) 2013 Avionic Design GmbH
+#
+# This software is provided 'as-is', without any express or implied
+# warranty. In no event will the authors be held liable for any damages
+# arising from the use of this software.
+#
+# Permission is granted to anyone to use this software for any purpose,
+# including commercial applications, and to alter it and redistribute it
+# freely, subject to the following restrictions:
+#
+# 1. The origin of this software must not be misrepresented; you must not
+#    claim that you wrote the original software. If you use this software
+#    in a product, an acknowledgment in the product documentation would be
+#    appreciated but is not required.
+# 2. Altered source versions must be plainly marked as such, and must not be
+#    misrepresented as being the original software.
+# 3. This notice may not be removed or altered from any source distribution.
+
+set -e
+set -x
+
+cbootimage -t30 -gbct \
+    ../tamonten-ng/TamontenNG_Nanya_1GB_NT5CC256M16CP-DI_750MHz_emmc.bct.cfg \
+    TamontenNG_Nanya_1GB_NT5CC256M16CP-DI_750MHz_emmc.bct
+cbootimage -t30 ../tamonten-ng/tegra30.img.cfg tegra30-tec-ng.img