Add Compulab TrimSlice configuration

This is based on CompuLab's own cbootimage scripts repo at
git://gitorious.org/cbootimage/cbootimage-scripts.git

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Change-Id: If83aa8e658e1853d253fd2bf760d48a642427c9c
Reviewed-on: http://git-master/r/190071
Reviewed-by: Allen Martin <amartin@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Eric Brower <ebrower@nvidia.com>

6 files changed, 380 insertions, 0 deletions

diff --git a/trimslice/README.txt b/trimslice/README.txt
new file mode 100644
index 0000000..6d9facd
--- /dev/null
+++ b/trimslice/README.txt
@@ -0,0 +1,25 @@
+The TrimSlice board is designed and sold by CompuLab, and is not an NVIDIA
+reference board. The configuration files here are graciously provided by
+CompuLab and relicensed with their permission for inclusion in this
+repository.
+
+The files in this directory were derived from CompuLab's repository,
+available at:
+
+git://gitorious.org/cbootimage/cbootimage-scripts.git
+
+The following repository also contains similar content:
+
+git://gitorious.org/cbootimage/cbootimage.git (branch trimslice)
+
+Changes made relative to cbootimage-scripts.git were:
+* Merged separate DDR and MMC, or DDR and SPI, config files into combined
+  files to simplify their usage, and added header variables such as Version,
+  BlockSize, etc.
+* Created image-generation config files.
+* Added OdmData, based on Compulab's U-Boot code, with debug UART value fixed
+  to be UART A not UART D.
+* Switched U-Boot load/entry address from 0x00e08000 to 0x00108000 to match
+  upstream U-Boot.
+* Set PreBctPadBlocks and Bctcopy for MMC, to match the recovery images
+  provided by Compulab.
diff --git a/trimslice/build.sh b/trimslice/build.sh
new file mode 100755
index 0000000..9b730c6
--- /dev/null
+++ b/trimslice/build.sh
@@ -0,0 +1,28 @@
+#!/bin/sh
+
+# Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+#
+# This software is provided 'as-is', without any express or implied
+# warranty. In no event will the authors be held liable for any damages
+# arising from the use of this software.
+#
+# Permission is granted to anyone to use this software for any purpose,
+# including commercial applications, and to alter it and redistribute it
+# freely, subject to the following restrictions:
+#
+# 1. The origin of this software must not be misrepresented; you must not
+#    claim that you wrote the original software. If you use this software
+#    in a product, an acknowledgment in the product documentation would be
+#    appreciated but is not required.
+# 2. Altered source versions must be plainly marked as such, and must not be
+#    misrepresented as being the original software.
+# 3. This notice may not be removed or altered from any source distribution.
+
+set -e
+set -x
+
+cbootimage -gbct trimslice-mmc.bct.cfg trimslice-mmc.bct
+cbootimage trimslice-mmc.img.cfg trimslice-mmc.img
+
+cbootimage -gbct trimslice-spi.bct.cfg trimslice-spi.bct
+cbootimage trimslice-spi.img.cfg trimslice-spi.img
diff --git a/trimslice/trimslice-mmc.bct.cfg b/trimslice/trimslice-mmc.bct.cfg
new file mode 100644
index 0000000..7926aa0
--- /dev/null
+++ b/trimslice/trimslice-mmc.bct.cfg
@@ -0,0 +1,149 @@
+# Copyright (c) 2013, CompuLab Ltd.  All rights reserved.
+#
+# Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+# See README.txt for a description of NVIDIA's changes relative to CompuLab's
+# original.
+#
+# This software is provided 'as-is', without any express or implied
+# warranty. In no event will the authors be held liable for any damages
+# arising from the use of this software.
+#
+# Permission is granted to anyone to use this software for any purpose,
+# including commercial applications, and to alter it and redistribute it
+# freely, subject to the following restrictions:
+#
+# 1. The origin of this software must not be misrepresented; you must not
+#    claim that you wrote the original software. If you use this software
+#    in a product, an acknowledgment in the product documentation would be
+#    appreciated but is not required.
+# 2. Altered source versions must be plainly marked as such, and must not be
+#    misrepresented as being the original software.
+# 3. This notice may not be removed or altered from any source distribution.
+
+Version       = 0x00020001;
+BlockSize     = 0x00004000;
+PageSize      = 0x00000200;
+PartitionSize = 0x01000000;
+OdmData       = 0x300c0000;
+
+DevType[0] = NvBootDevType_Sdmmc;
+DeviceParam[0].SdmmcParams.ClockDivider           = 0x0000000c;
+DeviceParam[0].SdmmcParams.DataWidth              = NvBootSdmmcDataWidth_4Bit;
+DeviceParam[0].SdmmcParams.MaxPowerClassSupported = 0x00000000;
+
+DevType[1] = NvBootDevType_Sdmmc;
+DeviceParam[1].SdmmcParams.ClockDivider           = 0x0000000c;
+DeviceParam[1].SdmmcParams.DataWidth              = NvBootSdmmcDataWidth_4Bit;
+DeviceParam[1].SdmmcParams.MaxPowerClassSupported = 0x00000000;
+
+DevType[2] = NvBootDevType_Sdmmc;
+DeviceParam[2].SdmmcParams.ClockDivider           = 0x0000000c;
+DeviceParam[2].SdmmcParams.DataWidth              = NvBootSdmmcDataWidth_4Bit;
+DeviceParam[2].SdmmcParams.MaxPowerClassSupported = 0x00000000;
+
+DevType[3] = NvBootDevType_Sdmmc;
+DeviceParam[3].SdmmcParams.ClockDivider           = 0x0000000c;
+DeviceParam[3].SdmmcParams.DataWidth              = NvBootSdmmcDataWidth_4Bit;
+DeviceParam[3].SdmmcParams.MaxPowerClassSupported = 0x00000000;
+
+SDRAM[0].MemoryType                 = NvBootMemoryType_Ddr2;
+SDRAM[0].PllMChargePumpSetupControl = 0x00000008;
+SDRAM[0].PllMLoopFilterSetupControl = 0x00000000;
+SDRAM[0].PllMInputDivider           = 0x0000000c;
+SDRAM[0].PllMFeedbackDivider        = 0x0000029a;
+SDRAM[0].PllMPostDivider            = 0x00000000;
+SDRAM[0].PllMStableTime             = 0x0000012c;
+SDRAM[0].EmcClockDivider            = 0x00000001;
+SDRAM[0].EmcAutoCalInterval         = 0x00000000;
+SDRAM[0].EmcAutoCalConfig           = 0xe0a61818;
+SDRAM[0].EmcAutoCalWait             = 0x00000000;
+SDRAM[0].EmcPinProgramWait          = 0x00000000;
+SDRAM[0].EmcRc                      = 0x00000014;
+SDRAM[0].EmcRfc                     = 0x0000002b;
+SDRAM[0].EmcRas                     = 0x0000000f;
+SDRAM[0].EmcRp                      = 0x00000005;
+SDRAM[0].EmcR2w                     = 0x00000004;
+SDRAM[0].EmcW2r                     = 0x00000005;
+SDRAM[0].EmcR2p                     = 0x00000003;
+SDRAM[0].EmcW2p                     = 0x0000000c;
+SDRAM[0].EmcRrd                     = 0x00000003;
+SDRAM[0].EmcRdRcd                   = 0x00000005;
+SDRAM[0].EmcWrRcd                   = 0x00000005;
+SDRAM[0].EmcRext                    = 0x00000001;
+SDRAM[0].EmcWdv                     = 0x00000004;
+SDRAM[0].EmcQUseExtra               = 0x00000000;
+SDRAM[0].EmcQUse                    = 0x00000005;
+SDRAM[0].EmcQRst                    = 0x00000004;
+SDRAM[0].EmcQSafe                   = 0x00000009;
+SDRAM[0].EmcRdv                     = 0x0000000d;
+SDRAM[0].EmcRefresh                 = 0x000009ff;
+SDRAM[0].EmcBurstRefreshNum         = 0x00000000;
+SDRAM[0].EmcPdEx2Wr                 = 0x00000003;
+SDRAM[0].EmcPdEx2Rd                 = 0x00000003;
+SDRAM[0].EmcPChg2Pden               = 0x00000005;
+SDRAM[0].EmcAct2Pden                = 0x00000005;
+SDRAM[0].EmcAr2Pden                 = 0x00000001;
+SDRAM[0].EmcRw2Pden                 = 0x0000000f;
+SDRAM[0].EmcTxsr                    = 0x000000c8;
+SDRAM[0].EmcTcke                    = 0x00000003;
+SDRAM[0].EmcTfaw                    = 0x0000000c;
+SDRAM[0].EmcTrpab                   = 0x00000006;
+SDRAM[0].EmcTClkStable              = 0x00000008;
+SDRAM[0].EmcTClkStop                = 0x00000002;
+SDRAM[0].EmcTRefBw                  = 0x00000000;
+SDRAM[0].EmcFbioCfg1                = 0x00000000;
+SDRAM[0].EmcFbioDqsibDlyMsb         = 0x00000000;
+SDRAM[0].EmcFbioDqsibDly            = 0x1c1c2020;
+SDRAM[0].EmcFbioQuseDlyMsb          = 0x00000000;
+SDRAM[0].EmcFbioQuseDly             = 0x5a504646;
+SDRAM[0].EmcFbioCfg5                = 0x00000083;
+SDRAM[0].EmcFbioCfg6                = 0x00000002;
+SDRAM[0].EmcFbioSpare               = 0x00000000;
+SDRAM[0].EmcMrsResetDllWait         = 0x00000000;
+SDRAM[0].EmcMrsResetDll             = 0x00000000;
+SDRAM[0].EmcMrsDdr2DllReset         = 0x00000100;
+SDRAM[0].EmcMrs                     = 0x00000a6a;
+SDRAM[0].EmcEmrsEmr2                = 0x00200000;
+SDRAM[0].EmcEmrsEmr3                = 0x00300000;
+SDRAM[0].EmcEmrsDdr2DllEnable       = 0x00100000;
+SDRAM[0].EmcEmrsDdr2OcdCalib        = 0x00100384;
+SDRAM[0].EmcEmrs                    = 0x00100004;
+SDRAM[0].EmcMrw1                    = 0x00000000;
+SDRAM[0].EmcMrw2                    = 0x00000000;
+SDRAM[0].EmcMrw3                    = 0x00000000;
+SDRAM[0].EmcMrwResetCommand         = 0x00000000;
+SDRAM[0].EmcMrwResetNInitWait       = 0x00000000;
+SDRAM[0].EmcAdrCfg1                 = 0x00070303;
+SDRAM[0].EmcAdrCfg                  = 0x01070303;
+SDRAM[0].McEmemCfg                  = 0x00100000;
+SDRAM[0].McLowLatencyConfig         = 0x80000003;
+SDRAM[0].EmcCfg2                    = 0x00000405;
+SDRAM[0].EmcCfgDigDll               = 0xf0000313;
+SDRAM[0].EmcCfgClktrim0             = 0x00000000;
+SDRAM[0].EmcCfgClktrim1             = 0x00000000;
+SDRAM[0].EmcCfgClktrim2             = 0x00000000;
+SDRAM[0].EmcCfg                     = 0x2001ff01;
+SDRAM[0].EmcDbg                     = 0x01000000;
+SDRAM[0].AhbArbitrationXbarCtrl     = 0x00010000;
+SDRAM[0].EmcDllXformDqs             = 0x00000010;
+SDRAM[0].EmcDllXformQUse            = 0x00000008;
+SDRAM[0].WarmBootWait               = 0x00000002;
+SDRAM[0].EmcCttTermCtrl             = 0x00000802;
+SDRAM[0].EmcOdtWrite                = 0x00000000;
+SDRAM[0].EmcOdtRead                 = 0x00000000;
+SDRAM[0].EmcZcalRefCnt              = 0x00000000;
+SDRAM[0].EmcZcalWaitCnt             = 0x00000000;
+SDRAM[0].EmcZcalMrwCmd              = 0x00000000;
+SDRAM[0].EmcMrwZqInitDev0           = 0x00000000;
+SDRAM[0].EmcMrwZqInitDev1           = 0x00000000;
+SDRAM[0].EmcMrwZqInitWait           = 0x00000000;
+SDRAM[0].EmcDdr2Wait                = 0x00000002;
+SDRAM[0].PmcDdrPwr                  = 0x00000001;
+SDRAM[0].ApbMiscGpXm2CfgAPadCtrl    = 0x77ffc000;
+SDRAM[0].ApbMiscGpXm2CfgCPadCtrl2   = 0x08080079;
+SDRAM[0].ApbMiscGpXm2CfgCPadCtrl    = 0x77fffff0;
+SDRAM[0].ApbMiscGpXm2CfgDPadCtrl2   = 0x44440009;
+SDRAM[0].ApbMiscGpXm2CfgDPadCtrl    = 0x77fffff0;
+SDRAM[0].ApbMiscGpXm2ClkCfgPadCtrl  = 0x77ffc000;
+SDRAM[0].ApbMiscGpXm2CompPadCtrl    = 0x01f1f008;
+SDRAM[0].ApbMiscGpXm2VttGenPadCtrl  = 0x07076600;
diff --git a/trimslice/trimslice-mmc.img.cfg b/trimslice/trimslice-mmc.img.cfg
new file mode 100644
index 0000000..95c4bdf
--- /dev/null
+++ b/trimslice/trimslice-mmc.img.cfg
@@ -0,0 +1,23 @@
+# Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+#
+# This software is provided 'as-is', without any express or implied
+# warranty. In no event will the authors be held liable for any damages
+# arising from the use of this software.
+#
+# Permission is granted to anyone to use this software for any purpose,
+# including commercial applications, and to alter it and redistribute it
+# freely, subject to the following restrictions:
+#
+# 1. The origin of this software must not be misrepresented; you must not
+#    claim that you wrote the original software. If you use this software
+#    in a product, an acknowledgment in the product documentation would be
+#    appreciated but is not required.
+# 2. Altered source versions must be plainly marked as such, and must not be
+#    misrepresented as being the original software.
+# 3. This notice may not be removed or altered from any source distribution.
+
+Version       = 0x00020001;
+PreBctPadBlocks = 8;
+Bctcopy       = 1;
+Bctfile       = trimslice-mmc.bct;
+BootLoader    = u-boot.bin,0x00108000,0x00108000,Complete;
diff --git a/trimslice/trimslice-spi.bct.cfg b/trimslice/trimslice-spi.bct.cfg
new file mode 100644
index 0000000..955100c
--- /dev/null
+++ b/trimslice/trimslice-spi.bct.cfg
@@ -0,0 +1,134 @@
+# Copyright (c) 2012, CompuLab Ltd.  All rights reserved.
+#
+# Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+# See README.txt for a description of NVIDIA's changes relative to CompuLab's
+# original.
+#
+# This software is provided 'as-is', without any express or implied
+# warranty. In no event will the authors be held liable for any damages
+# arising from the use of this software.
+#
+# Permission is granted to anyone to use this software for any purpose,
+# including commercial applications, and to alter it and redistribute it
+# freely, subject to the following restrictions:
+#
+# 1. The origin of this software must not be misrepresented; you must not
+#    claim that you wrote the original software. If you use this software
+#    in a product, an acknowledgment in the product documentation would be
+#    appreciated but is not required.
+# 2. Altered source versions must be plainly marked as such, and must not be
+#    misrepresented as being the original software.
+# 3. This notice may not be removed or altered from any source distribution.
+
+Version       = 0x00020001;
+BlockSize     = 0x00008000;
+PageSize      = 0x00000800;
+PartitionSize = 0x01000000;
+OdmData       = 0x300c0000;
+
+DevType[0] = NvBootDevType_Spi;
+DeviceParam[0].SpiFlashParams.ReadCommandTypeFast = 0;
+DeviceParam[0].SpiFlashParams.ClockDivider        = 12;
+DeviceParam[0].SpiFlashParams.ClockSource         = NvBootSpiClockSource_PllPOut0;
+
+SDRAM[0].MemoryType                 = NvBootMemoryType_Ddr2;
+SDRAM[0].PllMChargePumpSetupControl = 0x00000008;
+SDRAM[0].PllMLoopFilterSetupControl = 0x00000000;
+SDRAM[0].PllMInputDivider           = 0x0000000c;
+SDRAM[0].PllMFeedbackDivider        = 0x0000029a;
+SDRAM[0].PllMPostDivider            = 0x00000000;
+SDRAM[0].PllMStableTime             = 0x0000012c;
+SDRAM[0].EmcClockDivider            = 0x00000001;
+SDRAM[0].EmcAutoCalInterval         = 0x00000000;
+SDRAM[0].EmcAutoCalConfig           = 0xe0a61818;
+SDRAM[0].EmcAutoCalWait             = 0x00000000;
+SDRAM[0].EmcPinProgramWait          = 0x00000000;
+SDRAM[0].EmcRc                      = 0x00000014;
+SDRAM[0].EmcRfc                     = 0x0000002b;
+SDRAM[0].EmcRas                     = 0x0000000f;
+SDRAM[0].EmcRp                      = 0x00000005;
+SDRAM[0].EmcR2w                     = 0x00000004;
+SDRAM[0].EmcW2r                     = 0x00000005;
+SDRAM[0].EmcR2p                     = 0x00000003;
+SDRAM[0].EmcW2p                     = 0x0000000c;
+SDRAM[0].EmcRrd                     = 0x00000003;
+SDRAM[0].EmcRdRcd                   = 0x00000005;
+SDRAM[0].EmcWrRcd                   = 0x00000005;
+SDRAM[0].EmcRext                    = 0x00000001;
+SDRAM[0].EmcWdv                     = 0x00000004;
+SDRAM[0].EmcQUseExtra               = 0x00000000;
+SDRAM[0].EmcQUse                    = 0x00000005;
+SDRAM[0].EmcQRst                    = 0x00000004;
+SDRAM[0].EmcQSafe                   = 0x00000009;
+SDRAM[0].EmcRdv                     = 0x0000000d;
+SDRAM[0].EmcRefresh                 = 0x000009ff;
+SDRAM[0].EmcBurstRefreshNum         = 0x00000000;
+SDRAM[0].EmcPdEx2Wr                 = 0x00000003;
+SDRAM[0].EmcPdEx2Rd                 = 0x00000003;
+SDRAM[0].EmcPChg2Pden               = 0x00000005;
+SDRAM[0].EmcAct2Pden                = 0x00000005;
+SDRAM[0].EmcAr2Pden                 = 0x00000001;
+SDRAM[0].EmcRw2Pden                 = 0x0000000f;
+SDRAM[0].EmcTxsr                    = 0x000000c8;
+SDRAM[0].EmcTcke                    = 0x00000003;
+SDRAM[0].EmcTfaw                    = 0x0000000c;
+SDRAM[0].EmcTrpab                   = 0x00000006;
+SDRAM[0].EmcTClkStable              = 0x00000008;
+SDRAM[0].EmcTClkStop                = 0x00000002;
+SDRAM[0].EmcTRefBw                  = 0x00000000;
+SDRAM[0].EmcFbioCfg1                = 0x00000000;
+SDRAM[0].EmcFbioDqsibDlyMsb         = 0x00000000;
+SDRAM[0].EmcFbioDqsibDly            = 0x1c1c2020;
+SDRAM[0].EmcFbioQuseDlyMsb          = 0x00000000;
+SDRAM[0].EmcFbioQuseDly             = 0x5a504646;
+SDRAM[0].EmcFbioCfg5                = 0x00000083;
+SDRAM[0].EmcFbioCfg6                = 0x00000002;
+SDRAM[0].EmcFbioSpare               = 0x00000000;
+SDRAM[0].EmcMrsResetDllWait         = 0x00000000;
+SDRAM[0].EmcMrsResetDll             = 0x00000000;
+SDRAM[0].EmcMrsDdr2DllReset         = 0x00000100;
+SDRAM[0].EmcMrs                     = 0x00000a6a;
+SDRAM[0].EmcEmrsEmr2                = 0x00200000;
+SDRAM[0].EmcEmrsEmr3                = 0x00300000;
+SDRAM[0].EmcEmrsDdr2DllEnable       = 0x00100000;
+SDRAM[0].EmcEmrsDdr2OcdCalib        = 0x00100384;
+SDRAM[0].EmcEmrs                    = 0x00100004;
+SDRAM[0].EmcMrw1                    = 0x00000000;
+SDRAM[0].EmcMrw2                    = 0x00000000;
+SDRAM[0].EmcMrw3                    = 0x00000000;
+SDRAM[0].EmcMrwResetCommand         = 0x00000000;
+SDRAM[0].EmcMrwResetNInitWait       = 0x00000000;
+SDRAM[0].EmcAdrCfg1                 = 0x00070303;
+SDRAM[0].EmcAdrCfg                  = 0x01070303;
+SDRAM[0].McEmemCfg                  = 0x00100000;
+SDRAM[0].McLowLatencyConfig         = 0x80000003;
+SDRAM[0].EmcCfg2                    = 0x00000405;
+SDRAM[0].EmcCfgDigDll               = 0xf0000313;
+SDRAM[0].EmcCfgClktrim0             = 0x00000000;
+SDRAM[0].EmcCfgClktrim1             = 0x00000000;
+SDRAM[0].EmcCfgClktrim2             = 0x00000000;
+SDRAM[0].EmcCfg                     = 0x2001ff01;
+SDRAM[0].EmcDbg                     = 0x01000000;
+SDRAM[0].AhbArbitrationXbarCtrl     = 0x00010000;
+SDRAM[0].EmcDllXformDqs             = 0x00000010;
+SDRAM[0].EmcDllXformQUse            = 0x00000008;
+SDRAM[0].WarmBootWait               = 0x00000002;
+SDRAM[0].EmcCttTermCtrl             = 0x00000802;
+SDRAM[0].EmcOdtWrite                = 0x00000000;
+SDRAM[0].EmcOdtRead                 = 0x00000000;
+SDRAM[0].EmcZcalRefCnt              = 0x00000000;
+SDRAM[0].EmcZcalWaitCnt             = 0x00000000;
+SDRAM[0].EmcZcalMrwCmd              = 0x00000000;
+SDRAM[0].EmcMrwZqInitDev0           = 0x00000000;
+SDRAM[0].EmcMrwZqInitDev1           = 0x00000000;
+SDRAM[0].EmcMrwZqInitWait           = 0x00000000;
+SDRAM[0].EmcDdr2Wait                = 0x00000002;
+SDRAM[0].PmcDdrPwr                  = 0x00000001;
+SDRAM[0].ApbMiscGpXm2CfgAPadCtrl    = 0x77ffc000;
+SDRAM[0].ApbMiscGpXm2CfgCPadCtrl2   = 0x08080079;
+SDRAM[0].ApbMiscGpXm2CfgCPadCtrl    = 0x77fffff0;
+SDRAM[0].ApbMiscGpXm2CfgDPadCtrl2   = 0x44440009;
+SDRAM[0].ApbMiscGpXm2CfgDPadCtrl    = 0x77fffff0;
+SDRAM[0].ApbMiscGpXm2ClkCfgPadCtrl  = 0x77ffc000;
+SDRAM[0].ApbMiscGpXm2CompPadCtrl    = 0x01f1f008;
+SDRAM[0].ApbMiscGpXm2VttGenPadCtrl  = 0x07076600;
diff --git a/trimslice/trimslice-spi.img.cfg b/trimslice/trimslice-spi.img.cfg
new file mode 100644
index 0000000..2a2e685
--- /dev/null
+++ b/trimslice/trimslice-spi.img.cfg
@@ -0,0 +1,21 @@
+# Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+#
+# This software is provided 'as-is', without any express or implied
+# warranty. In no event will the authors be held liable for any damages
+# arising from the use of this software.
+#
+# Permission is granted to anyone to use this software for any purpose,
+# including commercial applications, and to alter it and redistribute it
+# freely, subject to the following restrictions:
+#
+# 1. The origin of this software must not be misrepresented; you must not
+#    claim that you wrote the original software. If you use this software
+#    in a product, an acknowledgment in the product documentation would be
+#    appreciated but is not required.
+# 2. Altered source versions must be plainly marked as such, and must not be
+#    misrepresented as being the original software.
+# 3. This notice may not be removed or altered from any source distribution.
+
+Version       = 0x00020001;
+Bctfile       = trimslice-spi.bct;
+BootLoader    = u-boot.bin,0x00108000,0x00108000,Complete;