diff options
Diffstat (limited to 'src/t132')
| -rw-r--r-- | src/t132/nvbctlib_t132.c | 78 | ||||
| -rw-r--r-- | src/t132/nvboot_bct_t132.h | 98 | ||||
| -rw-r--r-- | src/t132/nvboot_sdram_param_t132.h | 616 |
3 files changed, 396 insertions, 396 deletions
diff --git a/src/t132/nvbctlib_t132.c b/src/t132/nvbctlib_t132.c index ab5ab34..5f3af0f 100644 --- a/src/t132/nvbctlib_t132.c +++ b/src/t132/nvbctlib_t132.c @@ -60,22 +60,22 @@ case token_bl_##x:\ case token_##id:\ if (bct == NULL) \ return -ENODATA; \ - *((u_int32_t *)data) = bct_ptr->id; \ + *((uint32_t *)data) = bct_ptr->id; \ break #define CASE_GET_CONST(id, val) \ case token_##id:\ - *((u_int32_t *)data) = val; \ + *((uint32_t *)data) = val; \ break #define CASE_GET_CONST_PREFIX(id, val_prefix) \ case token_##id:\ - *((u_int32_t *)data) = val_prefix##_##id; \ + *((uint32_t *)data) = val_prefix##_##id; \ break #define CASE_SET_NVU32(id) \ case token_##id:\ - bct_ptr->id = *((u_int32_t *)data); \ + bct_ptr->id = *((uint32_t *)data); \ break #define CASE_GET_DATA(id, size) \ @@ -130,9 +130,9 @@ parse_token t132_root_token_list[] = { int t132_set_dev_param(build_image_context *context, - u_int32_t index, + uint32_t index, parse_token token, - u_int32_t value) + uint32_t value) { nvboot_config_table *bct = NULL; @@ -166,9 +166,9 @@ t132_set_dev_param(build_image_context *context, int t132_get_dev_param(build_image_context *context, - u_int32_t index, + uint32_t index, parse_token token, - u_int32_t *value) + uint32_t *value) { nvboot_config_table *bct = NULL; @@ -200,9 +200,9 @@ t132_get_dev_param(build_image_context *context, int t132_get_sdram_param(build_image_context *context, - u_int32_t index, + uint32_t index, parse_token token, - u_int32_t *value) + uint32_t *value) { nvboot_sdram_params *params; nvboot_config_table *bct = NULL; @@ -530,9 +530,9 @@ t132_get_sdram_param(build_image_context *context, int t132_set_sdram_param(build_image_context *context, - u_int32_t index, + uint32_t index, parse_token token, - u_int32_t value) + uint32_t value) { nvboot_sdram_params *params; nvboot_config_table *bct = NULL; @@ -861,10 +861,10 @@ t132_set_sdram_param(build_image_context *context, } int -t132_getbl_param(u_int32_t set, +t132_getbl_param(uint32_t set, parse_token id, - u_int32_t *data, - u_int8_t *bct) + uint32_t *data, + uint8_t *bct) { nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; @@ -896,10 +896,10 @@ t132_getbl_param(u_int32_t set, } int -t132_setbl_param(u_int32_t set, +t132_setbl_param(uint32_t set, parse_token id, - u_int32_t *data, - u_int8_t *bct) + uint32_t *data, + uint8_t *bct) { nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; @@ -931,7 +931,7 @@ t132_setbl_param(u_int32_t set, } int -t132_bct_get_value(parse_token id, void *data, u_int8_t *bct) +t132_bct_get_value(parse_token id, void *data, uint8_t *bct) { nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; nvboot_config_table samplebct; /* Used for computing offsets. */ @@ -960,19 +960,19 @@ t132_bct_get_value(parse_token id, void *data, u_int8_t *bct) case token_block_size: if (bct == NULL) return -ENODATA; - *((u_int32_t *)data) = 1 << bct_ptr->block_size_log2; + *((uint32_t *)data) = 1 << bct_ptr->block_size_log2; break; case token_page_size: if (bct == NULL) return -ENODATA; - *((u_int32_t *)data) = 1 << bct_ptr->page_size_log2; + *((uint32_t *)data) = 1 << bct_ptr->page_size_log2; break; case token_mts_used: if (bct == NULL) return -ENODATA; - *((u_int32_t *)data) = bct_ptr->mts_boot_components_used; + *((uint32_t *)data) = bct_ptr->mts_boot_components_used; break; /* @@ -994,26 +994,26 @@ t132_bct_get_value(parse_token id, void *data, u_int8_t *bct) break; case token_reserved_offset: - *((u_int32_t *)data) = (u_int8_t *)&(samplebct.reserved) - - (u_int8_t *)&samplebct; + *((uint32_t *)data) = (uint8_t *)&(samplebct.reserved) + - (uint8_t *)&samplebct; break; case token_bct_size: - *((u_int32_t *)data) = sizeof(nvboot_config_table); + *((uint32_t *)data) = sizeof(nvboot_config_table); break; CASE_GET_CONST(hash_size, sizeof(nvboot_hash)); case token_crypto_offset: /* Offset to region in BCT to encrypt & sign */ - *((u_int32_t *)data) = (u_int8_t *)&(samplebct.random_aes_blk) - - (u_int8_t *)&samplebct; + *((uint32_t *)data) = (uint8_t *)&(samplebct.random_aes_blk) + - (uint8_t *)&samplebct; break; case token_crypto_length: /* size of region in BCT to encrypt & sign */ - *((u_int32_t *)data) = (u_int8_t *)bct_ptr + sizeof(nvboot_config_table) - - (u_int8_t *)&(bct_ptr->random_aes_blk); + *((uint32_t *)data) = (uint8_t *)bct_ptr + sizeof(nvboot_config_table) + - (uint8_t *)&(bct_ptr->random_aes_blk); break; CASE_GET_CONST(max_bct_search_blks, NVBOOT_MAX_BCT_SEARCH_BLOCKS); @@ -1039,7 +1039,7 @@ t132_bct_get_value(parse_token id, void *data, u_int8_t *bct) } int -t132_bct_set_value(parse_token id, void *data, u_int8_t *bct) +t132_bct_set_value(parse_token id, void *data, uint8_t *bct) { nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; @@ -1064,7 +1064,7 @@ t132_bct_set_value(parse_token id, void *data, u_int8_t *bct) break; case token_mts_used: - bct_ptr->mts_boot_components_used = *((u_int32_t *)data); + bct_ptr->mts_boot_components_used = *((uint32_t *)data); break; default: @@ -1076,9 +1076,9 @@ t132_bct_set_value(parse_token id, void *data, u_int8_t *bct) int t132_bct_set_data(parse_token id, - u_int8_t *data, - u_int32_t length, - u_int8_t *bct) + uint8_t *data, + uint32_t length, + uint8_t *bct) { nvboot_config_table *bct_ptr = (nvboot_config_table *)bct; @@ -1107,9 +1107,9 @@ int t132_get_bct_size() int t132_set_mts_info(build_image_context *context, - u_int32_t index, + uint32_t index, parse_token token, - u_int32_t value) + uint32_t value) { nvboot_mts_info *mts_info; nvboot_config_table *bct = NULL; @@ -1135,9 +1135,9 @@ t132_set_mts_info(build_image_context *context, int t132_get_mts_info(build_image_context *context, - u_int32_t index, + uint32_t index, parse_token token, - u_int32_t *value) + uint32_t *value) { nvboot_mts_info *mts_info; nvboot_config_table *bct = NULL; @@ -1174,7 +1174,7 @@ int t132_bct_token_supported(parse_token token) void t132_init_bad_block_table(build_image_context *context) { - u_int32_t bytes_per_entry; + uint32_t bytes_per_entry; nvboot_badblock_table *table; nvboot_config_table *bct; diff --git a/src/t132/nvboot_bct_t132.h b/src/t132/nvboot_bct_t132.h index 8c6fd6b..7dc0bf2 100644 --- a/src/t132/nvboot_bct_t132.h +++ b/src/t132/nvboot_bct_t132.h @@ -115,7 +115,7 @@ enum {NVBOOT_CMAC_AES_HASH_LENGTH = 4}; * Defines the storage for a hash value (128 bits). */ typedef struct nvboot_hash_rec { - u_int32_t hash[NVBOOT_CMAC_AES_HASH_LENGTH]; + uint32_t hash[NVBOOT_CMAC_AES_HASH_LENGTH]; } nvboot_hash; /* @@ -124,7 +124,7 @@ typedef struct nvboot_hash_rec { */ typedef struct nvboot_rsa_key_modulus_rec { /* The modulus size is 2048-bits. */ - u_int32_t modulus[NVBOOT_SE_RSA_MODULUS_LENGTH_BITS / 8 / 4]; + uint32_t modulus[NVBOOT_SE_RSA_MODULUS_LENGTH_BITS / 8 / 4]; } nvboot_rsa_key_modulus; typedef struct nvboot_rsa_pss_sig_rec { @@ -133,7 +133,7 @@ typedef struct nvboot_rsa_pss_sig_rec { * length in octets of the RSA modulus. * In our case, it's 2048-bits. */ - u_int32_t signature[NVBOOT_SE_RSA_MODULUS_LENGTH_BITS / 8 / 4]; + uint32_t signature[NVBOOT_SE_RSA_MODULUS_LENGTH_BITS / 8 / 4]; } nvboot_rsa_pss_sig; typedef struct nvboot_object_signature_rec { @@ -151,10 +151,10 @@ typedef struct nvboot_object_signature_rec { } nvboot_object_signature; typedef struct nvboot_ecid_rec { - u_int32_t ecid_0; - u_int32_t ecid_1; - u_int32_t ecid_2; - u_int32_t ecid_3; + uint32_t ecid_0; + uint32_t ecid_1; + uint32_t ecid_2; + uint32_t ecid_3; } nvboot_ecid; /* Defines various data widths supported. */ @@ -191,7 +191,7 @@ typedef struct nvboot_sdmmc_params_rec { * which is PLLP running at 216MHz. If it is set to 9, then the SDMMC * controller runs at 216/9 = 24MHz. */ - u_int8_t clock_divider; + uint8_t clock_divider; /* Specifies the data bus width. Supported data widths are 4/8 bits. */ nvboot_sdmmc_data_width data_width; @@ -202,10 +202,10 @@ typedef struct nvboot_sdmmc_params_rec { * supported within the power class range (0 to Max) if the selected * data width cannot be used at the chosen clock frequency. */ - u_int8_t max_power_class_supported; + uint8_t max_power_class_supported; /* Specifies the max page size supported by driver */ - u_int8_t multi_page_support; + uint8_t multi_page_support; } nvboot_sdmmc_params; typedef enum { @@ -226,7 +226,7 @@ typedef struct nvboot_spiflash_params_rec { /** * Specifies the clock source to use. */ - u_int32_t clock_source; + uint32_t clock_source; /** * Specifes the clock divider to use. @@ -238,24 +238,24 @@ typedef struct nvboot_spiflash_params_rec { * FAST_READ at 40MHz: 11 * FAST_READ at 50MHz: 9 */ - u_int8_t clock_divider; + uint8_t clock_divider; /** * Specifies the type of command for read operations. * NV_FALSE specifies a NORMAL_READ Command * NV_TRUE specifies a FAST_READ Command */ - u_int8_t read_command_type_fast; + uint8_t read_command_type_fast; /* 0 = 2k page size, 1 = 16K page size */ - u_int8_t page_size_2k_or_16k; + uint8_t page_size_2k_or_16k; } nvboot_spiflash_params; /** * Defines the union of the parameters required by each device. */ typedef union { - u_int8_t size[64]; + uint8_t size[64]; /* Specifies optimized parameters for eMMC and eSD */ nvboot_sdmmc_params sdmmc_params; /* Specifies optimized parameters for SPI NOR */ @@ -296,20 +296,20 @@ typedef struct nvboot_mts_info_rec * Specifies a version number for the MTS image. The assignment of * numbers is arbitrary; the numbers are only used to identify redundant. */ - u_int32_t version; + uint32_t version; /* * Specifies the first physical block on the secondary boot device * that contains the start of the MTS image. The first block can never be * a known bad block. */ - u_int32_t start_blk; + uint32_t start_blk; /* * Specifies the page within the first block that contains the start * of the MTS image. */ - u_int32_t start_page; + uint32_t start_page; /* * Specifies the length of the MTS image in bytes. MTS image must be @@ -318,22 +318,22 @@ typedef struct nvboot_mts_info_rec * a page. Add another 16 bytes to work around this restriction if * needed. */ - u_int32_t length; + uint32_t length; /* * Specifies the starting address of the memory region into which the * MTS will be loaded. This is optional. */ - u_int32_t load_addr; + uint32_t load_addr; /* Specifies the entry point address in the loaded MTS image. Optional */ - u_int32_t entry_point; + uint32_t entry_point; /* * Specifies an attribute available for use by other code. * Not interpreted by the Boot ROM. */ - u_int32_t attribute; + uint32_t attribute; } nvboot_mts_info; @@ -344,13 +344,13 @@ typedef struct nvboot_mts_info_rec * the device. */ typedef struct nv_bootloader_info_rec { - u_int32_t version; - u_int32_t start_blk; - u_int32_t start_page; - u_int32_t length; - u_int32_t load_addr; - u_int32_t entry_point; - u_int32_t attribute; + uint32_t version; + uint32_t start_blk; + uint32_t start_page; + uint32_t length; + uint32_t load_addr; + uint32_t entry_point; + uint32_t attribute; /* Specifies the AES-CMAC MAC or RSASSA-PSS signature of the BL. */ nvboot_object_signature signature; @@ -360,15 +360,15 @@ typedef struct nv_bootloader_info_rec { * Defines the bad block table structure stored in the BCT. */ typedef struct nvboot_badblock_table_rec { - u_int32_t entries_used; - u_int8_t virtual_blk_size_log2; - u_int8_t block_size_log2; - u_int8_t bad_blks[NVBOOT_BAD_BLOCK_TABLE_SIZE / 8]; + uint32_t entries_used; + uint8_t virtual_blk_size_log2; + uint8_t block_size_log2; + uint8_t bad_blks[NVBOOT_BAD_BLOCK_TABLE_SIZE / 8]; /* * Add a reserved field as padding to make the bad block table structure * a multiple of 16 bytes (AES block size). */ - u_int8_t reserved[NVBOOT_BAD_BLOCK_TABLE_PADDING]; + uint8_t reserved[NVBOOT_BAD_BLOCK_TABLE_PADDING]; } nvboot_badblock_table; /** @@ -383,31 +383,31 @@ typedef struct nvboot_config_table_rec { nvboot_badblock_table badblock_table; nvboot_rsa_key_modulus key; nvboot_object_signature signature; - u_int8_t customer_data[NVBOOT_BCT_CUSTOMER_DATA_SIZE]; - u_int32_t odm_data; - u_int32_t reserved1; + uint8_t customer_data[NVBOOT_BCT_CUSTOMER_DATA_SIZE]; + uint32_t odm_data; + uint32_t reserved1; /* START OF SIGNED SECTION OF THE BCT */ nvboot_hash random_aes_blk; nvboot_ecid unique_chip_id; - u_int32_t boot_data_version; - u_int32_t block_size_log2; - u_int32_t page_size_log2; - u_int32_t partition_size; - u_int32_t num_param_sets; + uint32_t boot_data_version; + uint32_t block_size_log2; + uint32_t page_size_log2; + uint32_t partition_size; + uint32_t num_param_sets; nvboot_dev_type dev_type[NVBOOT_BCT_MAX_PARAM_SETS]; nvboot_dev_params dev_params[NVBOOT_BCT_MAX_PARAM_SETS]; - u_int32_t num_sdram_sets; + uint32_t num_sdram_sets; nvboot_sdram_params sdram_params[NVBOOT_BCT_MAX_SDRAM_SETS]; - u_int32_t bootloader_used; + uint32_t bootloader_used; nv_bootloader_info bootloader[NVBOOT_MAX_BOOTLOADERS]; /* * Specify the number of Mts boot components described in the mts boot * table. */ - u_int32_t mts_boot_components_used; + uint32_t mts_boot_components_used; /* * Specify the information needed to locate and validate Denver Boot. @@ -416,7 +416,7 @@ typedef struct nvboot_config_table_rec { */ nvboot_mts_info mts_boot_components[NVBOOT_MAX_MTS_COMPONENTS]; - u_int8_t enable_fail_back; + uint8_t enable_fail_back; /* * Specify whether or not to enable JTAG access when the JTAG disable fuse @@ -424,15 +424,15 @@ typedef struct nvboot_config_table_rec { * secure_jtag_control = NV_FALSE (0) = Disable JTAG access. * secure_jtag_control = NV_TRUE (1) = Enable JTAG access. */ - u_int8_t secure_jtag_control; + uint8_t secure_jtag_control; /* * Specify whether or not to enable denver dfd access * cust_denver_dfd_en = NV_FALSE (0) = Disable Dfd access. * cust_denver_dfd_en = NV_TRUE (1) = Enable Dfd access. */ - u_int8_t cust_denver_dfd_en; + uint8_t cust_denver_dfd_en; - u_int8_t reserved[NVBOOT_BCT_RESERVED_SIZE]; + uint8_t reserved[NVBOOT_BCT_RESERVED_SIZE]; } nvboot_config_table; #endif /* #ifndef INCLUDED_NVBOOT_BCT_T132_H */ diff --git a/src/t132/nvboot_sdram_param_t132.h b/src/t132/nvboot_sdram_param_t132.h index 32629ce..166764a 100644 --- a/src/t132/nvboot_sdram_param_t132.h +++ b/src/t132/nvboot_sdram_param_t132.h @@ -63,436 +63,436 @@ typedef struct nvboot_sdram_params_rec { /* MC/EMC clock source configuration */ /* Specifies the M value for PllM */ - u_int32_t pllm_input_divider; + uint32_t pllm_input_divider; /* Specifies the N value for PllM */ - u_int32_t pllm_feedback_divider; + uint32_t pllm_feedback_divider; /* Specifies the time to wait for PLLM to lock (in microseconds) */ - u_int32_t pllm_stable_time; + uint32_t pllm_stable_time; /* Specifies misc. control bits */ - u_int32_t pllm_setup_control; + uint32_t pllm_setup_control; /* Enables the Div by 2 */ - u_int32_t pllm_select_div2; + uint32_t pllm_select_div2; /* Powers down VCO output Level shifter */ - u_int32_t pllm_pdlshift_ph45; + uint32_t pllm_pdlshift_ph45; /* Powers down VCO output Level shifter */ - u_int32_t pllm_pdlshift_ph90; + uint32_t pllm_pdlshift_ph90; /* Powers down VCO output Level shifter */ - u_int32_t pllm_pdlshift_ph135; + uint32_t pllm_pdlshift_ph135; /* Specifies value for Charge Pump Gain Control */ - u_int32_t pllm_kcp; + uint32_t pllm_kcp; /* Specifies VCO gain */ - u_int32_t pllm_kvco; + uint32_t pllm_kvco; /* Spare BCT param */ - u_int32_t emc_bct_spare0; + uint32_t emc_bct_spare0; /* Spare BCT param */ - u_int32_t emc_bct_spare1; + uint32_t emc_bct_spare1; /* Spare BCT param */ - u_int32_t emc_bct_spare2; + uint32_t emc_bct_spare2; /* Spare BCT param */ - u_int32_t emc_bct_spare3; + uint32_t emc_bct_spare3; /* Spare BCT param */ - u_int32_t emc_bct_spare4; + uint32_t emc_bct_spare4; /* Spare BCT param */ - u_int32_t emc_bct_spare5; + uint32_t emc_bct_spare5; /* Spare BCT param */ - u_int32_t emc_bct_spare6; + uint32_t emc_bct_spare6; /* Spare BCT param */ - u_int32_t emc_bct_spare7; + uint32_t emc_bct_spare7; /* Spare BCT param */ - u_int32_t emc_bct_spare8; + uint32_t emc_bct_spare8; /* Spare BCT param */ - u_int32_t emc_bct_spare9; + uint32_t emc_bct_spare9; /* Spare BCT param */ - u_int32_t emc_bct_spare10; + uint32_t emc_bct_spare10; /* Spare BCT param */ - u_int32_t emc_bct_spare11; + uint32_t emc_bct_spare11; /* Defines EMC_2X_CLK_SRC, EMC_2X_CLK_DIVISOR, EMC_INVERT_DCD */ - u_int32_t emc_clock_source; + uint32_t emc_clock_source; /* Auto-calibration of EMC pads */ /* Specifies the value for EMC_AUTO_CAL_INTERVAL */ - u_int32_t emc_auto_cal_interval; + uint32_t emc_auto_cal_interval; /* * Specifies the value for EMC_AUTO_CAL_CONFIG * Note: Trigger bits are set by the SDRAM code. */ - u_int32_t emc_auto_cal_config; + uint32_t emc_auto_cal_config; /* Specifies the value for EMC_AUTO_CAL_CONFIG2 */ - u_int32_t emc_auto_cal_config2; + uint32_t emc_auto_cal_config2; /* Specifies the value for EMC_AUTO_CAL_CONFIG3 */ - u_int32_t emc_auto_cal_config3; + uint32_t emc_auto_cal_config3; /* * Specifies the time for the calibration * to stabilize (in microseconds) */ - u_int32_t emc_auto_cal_wait; + uint32_t emc_auto_cal_wait; /* * DRAM size information * Specifies the value for EMC_ADR_CFG */ - u_int32_t emc_adr_cfg; + uint32_t emc_adr_cfg; /* * Specifies the time to wait after asserting pin * CKE (in microseconds) */ - u_int32_t emc_pin_program_wait; + uint32_t emc_pin_program_wait; /* Specifies the extra delay before/after pin RESET/CKE command */ - u_int32_t emc_pin_extra_wait; + uint32_t emc_pin_extra_wait; /* * Specifies the extra delay after the first writing * of EMC_TIMING_CONTROL */ - u_int32_t emc_timing_control_wait; + uint32_t emc_timing_control_wait; /* Timing parameters required for the SDRAM */ /* Specifies the value for EMC_RC */ - u_int32_t emc_rc; + uint32_t emc_rc; /* Specifies the value for EMC_RFC */ - u_int32_t emc_rfc; + uint32_t emc_rfc; /* Specifies the value for EMC_RFC_SLR */ - u_int32_t emc_rfc_slr; + uint32_t emc_rfc_slr; /* Specifies the value for EMC_RAS */ - u_int32_t emc_ras; + uint32_t emc_ras; /* Specifies the value for EMC_RP */ - u_int32_t emc_rp; + uint32_t emc_rp; /* Specifies the value for EMC_R2R */ - u_int32_t emc_r2r; + uint32_t emc_r2r; /* Specifies the value for EMC_W2W */ - u_int32_t emc_w2w; + uint32_t emc_w2w; /* Specifies the value for EMC_R2W */ - u_int32_t emc_r2w; + uint32_t emc_r2w; /* Specifies the value for EMC_W2R */ - u_int32_t emc_w2r; + uint32_t emc_w2r; /* Specifies the value for EMC_R2P */ - u_int32_t emc_r2p; + uint32_t emc_r2p; /* Specifies the value for EMC_W2P */ - u_int32_t emc_w2p; + uint32_t emc_w2p; /* Specifies the value for EMC_RD_RCD */ - u_int32_t emc_rd_rcd; + uint32_t emc_rd_rcd; /* Specifies the value for EMC_WR_RCD */ - u_int32_t emc_wr_rcd; + uint32_t emc_wr_rcd; /* Specifies the value for EMC_RRD */ - u_int32_t emc_rrd; + uint32_t emc_rrd; /* Specifies the value for EMC_REXT */ - u_int32_t emc_rext; + uint32_t emc_rext; /* Specifies the value for EMC_WEXT */ - u_int32_t emc_wext; + uint32_t emc_wext; /* Specifies the value for EMC_WDV */ - u_int32_t emc_wdv; + uint32_t emc_wdv; /* Specifies the value for EMC_WDV_MASK */ - u_int32_t emc_wdv_mask; + uint32_t emc_wdv_mask; /* Specifies the value for EMC_QUSE */ - u_int32_t emc_quse; + uint32_t emc_quse; /* Specifies the value for EMC_QUSE_WIDTH */ - u_int32_t emc_quse_width; + uint32_t emc_quse_width; /* Specifies the value for EMC_IBDLY */ - u_int32_t emc_ibdly; + uint32_t emc_ibdly; /* Specifies the value for EMC_EINPUT */ - u_int32_t emc_einput; + uint32_t emc_einput; /* Specifies the value for EMC_EINPUT_DURATION */ - u_int32_t emc_einput_duration; + uint32_t emc_einput_duration; /* Specifies the value for EMC_PUTERM_EXTRA */ - u_int32_t emc_puterm_extra; + uint32_t emc_puterm_extra; /* Specifies the value for EMC_PUTERM_WIDTH */ - u_int32_t emc_puterm_width; + uint32_t emc_puterm_width; /* Specifies the value for EMC_PUTERM_ADJ */ - u_int32_t emc_puterm_adj; + uint32_t emc_puterm_adj; /* Specifies the value for EMC_CDB_CNTL_1 */ - u_int32_t emc_cdb_cntl1; + uint32_t emc_cdb_cntl1; /* Specifies the value for EMC_CDB_CNTL_2 */ - u_int32_t emc_cdb_cntl2; + uint32_t emc_cdb_cntl2; /* Specifies the value for EMC_CDB_CNTL_3 */ - u_int32_t emc_cdb_cntl3; + uint32_t emc_cdb_cntl3; /* Specifies the value for EMC_QRST */ - u_int32_t emc_qrst; + uint32_t emc_qrst; /* Specifies the value for EMC_QSAFE */ - u_int32_t emc_qsafe; + uint32_t emc_qsafe; /* Specifies the value for EMC_RDV */ - u_int32_t emc_rdv; + uint32_t emc_rdv; /* Specifies the value for EMC_RDV_MASK */ - u_int32_t emc_rdv_mask; + uint32_t emc_rdv_mask; /* Specifies the value for EMC_QPOP */ - u_int32_t emc_qpop; + uint32_t emc_qpop; /* Specifies the value for EMC_CTT */ - u_int32_t emc_ctt; + uint32_t emc_ctt; /* Specifies the value for EMC_CTT_DURATION */ - u_int32_t emc_ctt_duration; + uint32_t emc_ctt_duration; /* Specifies the value for EMC_REFRESH */ - u_int32_t emc_refresh; + uint32_t emc_refresh; /* Specifies the value for EMC_BURST_REFRESH_NUM */ - u_int32_t emc_burst_refresh_num; + uint32_t emc_burst_refresh_num; /* Specifies the value for EMC_PRE_REFRESH_REQ_CNT */ - u_int32_t emc_prerefresh_req_cnt; + uint32_t emc_prerefresh_req_cnt; /* Specifies the value for EMC_PDEX2WR */ - u_int32_t emc_pdex2wr; + uint32_t emc_pdex2wr; /* Specifies the value for EMC_PDEX2RD */ - u_int32_t emc_pdex2rd; + uint32_t emc_pdex2rd; /* Specifies the value for EMC_PCHG2PDEN */ - u_int32_t emc_pchg2pden; + uint32_t emc_pchg2pden; /* Specifies the value for EMC_ACT2PDEN */ - u_int32_t emc_act2pden; + uint32_t emc_act2pden; /* Specifies the value for EMC_AR2PDEN */ - u_int32_t emc_ar2pden; + uint32_t emc_ar2pden; /* Specifies the value for EMC_RW2PDEN */ - u_int32_t emc_rw2pden; + uint32_t emc_rw2pden; /* Specifies the value for EMC_TXSR */ - u_int32_t emc_txsr; + uint32_t emc_txsr; /* Specifies the value for EMC_TXSRDLL */ - u_int32_t emc_txsr_dll; + uint32_t emc_txsr_dll; /* Specifies the value for EMC_TCKE */ - u_int32_t emc_tcke; + uint32_t emc_tcke; /* Specifies the value for EMC_TCKESR */ - u_int32_t emc_tckesr; + uint32_t emc_tckesr; /* Specifies the value for EMC_TPD */ - u_int32_t emc_tpd; + uint32_t emc_tpd; /* Specifies the value for EMC_TFAW */ - u_int32_t emc_tfaw; + uint32_t emc_tfaw; /* Specifies the value for EMC_TRPAB */ - u_int32_t emc_trpab; + uint32_t emc_trpab; /* Specifies the value for EMC_TCLKSTABLE */ - u_int32_t emc_tclkstable; + uint32_t emc_tclkstable; /* Specifies the value for EMC_TCLKSTOP */ - u_int32_t emc_tclkstop; + uint32_t emc_tclkstop; /* Specifies the value for EMC_TREFBW */ - u_int32_t emc_trefbw; + uint32_t emc_trefbw; /* FBIO configuration values */ /* Specifies the value for EMC_FBIO_CFG5 */ - u_int32_t emc_fbio_cfg5; + uint32_t emc_fbio_cfg5; /* Specifies the value for EMC_FBIO_CFG6 */ - u_int32_t emc_fbio_cfg6; + uint32_t emc_fbio_cfg6; /* Specifies the value for EMC_FBIO_SPARE */ - u_int32_t emc_fbio_spare; + uint32_t emc_fbio_spare; /* Specifies the value for EMC_CFG_RSV */ - u_int32_t emc_cfg_rsv; + uint32_t emc_cfg_rsv; /* MRS command values */ /* Specifies the value for EMC_MRS */ - u_int32_t emc_mrs; + uint32_t emc_mrs; /* Specifies the MP0 command to initialize mode registers */ - u_int32_t emc_emrs; + uint32_t emc_emrs; /* Specifies the MP2 command to initialize mode registers */ - u_int32_t emc_emrs2; + uint32_t emc_emrs2; /* Specifies the MP3 command to initialize mode registers */ - u_int32_t emc_emrs3; + uint32_t emc_emrs3; /* Specifies the programming to LPDDR2 Mode Register 1 at cold boot */ - u_int32_t emc_mrw1; + uint32_t emc_mrw1; /* Specifies the programming to LPDDR2 Mode Register 2 at cold boot */ - u_int32_t emc_mrw2; + uint32_t emc_mrw2; /* Specifies the programming to LPDDR2 Mode Register 3 at cold boot */ - u_int32_t emc_mrw3; + uint32_t emc_mrw3; /* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */ - u_int32_t emc_mrw4; + uint32_t emc_mrw4; /* * Specifies the programming to extra LPDDR2 Mode Register * at cold boot */ - u_int32_t emc_mrw_extra; + uint32_t emc_mrw_extra; /* * Specifies the programming to extra LPDDR2 Mode Register * at warm boot */ - u_int32_t emc_warm_boot_mrw_extra; + uint32_t emc_warm_boot_mrw_extra; /* * Specify the enable of extra Mode Register programming at * warm boot */ - u_int32_t emc_warm_boot_extramode_reg_write_enable; + uint32_t emc_warm_boot_extramode_reg_write_enable; /* * Specify the enable of extra Mode Register programming at * cold boot */ - u_int32_t emc_extramode_reg_write_enable; + uint32_t emc_extramode_reg_write_enable; /* Specifies the EMC_MRW reset command value */ - u_int32_t emc_mrw_reset_command; + uint32_t emc_mrw_reset_command; /* Specifies the EMC Reset wait time (in microseconds) */ - u_int32_t emc_mrw_reset_ninit_wait; + uint32_t emc_mrw_reset_ninit_wait; /* Specifies the value for EMC_MRS_WAIT_CNT */ - u_int32_t emc_mrs_wait_cnt; + uint32_t emc_mrs_wait_cnt; /* Specifies the value for EMC_MRS_WAIT_CNT2 */ - u_int32_t emc_mrs_wait_cnt2; + uint32_t emc_mrs_wait_cnt2; /* EMC miscellaneous configurations */ /* Specifies the value for EMC_CFG */ - u_int32_t emc_cfg; + uint32_t emc_cfg; /* Specifies the value for EMC_CFG_2 */ - u_int32_t emc_cfg2; + uint32_t emc_cfg2; /* Specifies the pipe bypass controls */ - u_int32_t emc_cfg_pipe; + uint32_t emc_cfg_pipe; /* Specifies the value for EMC_DBG */ - u_int32_t emc_dbg; + uint32_t emc_dbg; /* Specifies the value for EMC_CMDQ */ - u_int32_t emc_cmd_q; + uint32_t emc_cmd_q; /* Specifies the value for EMC_MC2EMCQ */ - u_int32_t emc_mc2emc_q; + uint32_t emc_mc2emc_q; /* Specifies the value for EMC_DYN_SELF_REF_CONTROL */ - u_int32_t emc_dyn_self_ref_control; + uint32_t emc_dyn_self_ref_control; /* Specifies the value for MEM_INIT_DONE */ - u_int32_t ahb_arbitration_xbar_ctrl_meminit_done; + uint32_t ahb_arbitration_xbar_ctrl_meminit_done; /* Specifies the value for EMC_CFG_DIG_DLL */ - u_int32_t emc_cfg_dig_dll; + uint32_t emc_cfg_dig_dll; /* Specifies the value for EMC_CFG_DIG_DLL_PERIOD */ - u_int32_t emc_cfg_dig_dll_period; + uint32_t emc_cfg_dig_dll_period; /* Specifies the value of *DEV_SELECTN of various EMC registers */ - u_int32_t emc_dev_select; + uint32_t emc_dev_select; /* Specifies the value for EMC_SEL_DPD_CTRL */ - u_int32_t emc_sel_dpd_ctrl; + uint32_t emc_sel_dpd_ctrl; /* Pads trimmer delays */ /* Specifies the value for EMC_DLL_XFORM_DQS0 */ - u_int32_t emc_dll_xform_dqs0; + uint32_t emc_dll_xform_dqs0; /* Specifies the value for EMC_DLL_XFORM_DQS1 */ - u_int32_t emc_dll_xform_dqs1; + uint32_t emc_dll_xform_dqs1; /* Specifies the value for EMC_DLL_XFORM_DQS2 */ - u_int32_t emc_dll_xform_dqs2; + uint32_t emc_dll_xform_dqs2; /* Specifies the value for EMC_DLL_XFORM_DQS3 */ - u_int32_t emc_dll_xform_dqs3; + uint32_t emc_dll_xform_dqs3; /* Specifies the value for EMC_DLL_XFORM_DQS4 */ - u_int32_t emc_dll_xform_dqs4; + uint32_t emc_dll_xform_dqs4; /* Specifies the value for EMC_DLL_XFORM_DQS5 */ - u_int32_t emc_dll_xform_dqs5; + uint32_t emc_dll_xform_dqs5; /* Specifies the value for EMC_DLL_XFORM_DQS6 */ - u_int32_t emc_dll_xform_dqs6; + uint32_t emc_dll_xform_dqs6; /* Specifies the value for EMC_DLL_XFORM_DQS7 */ - u_int32_t emc_dll_xform_dqs7; + uint32_t emc_dll_xform_dqs7; /* Specifies the value for EMC_DLL_XFORM_DQS8 */ - u_int32_t emc_dll_xform_dqs8; + uint32_t emc_dll_xform_dqs8; /* Specifies the value for EMC_DLL_XFORM_DQS9 */ - u_int32_t emc_dll_xform_dqs9; + uint32_t emc_dll_xform_dqs9; /* Specifies the value for EMC_DLL_XFORM_DQS10 */ - u_int32_t emc_dll_xform_dqs10; + uint32_t emc_dll_xform_dqs10; /* Specifies the value for EMC_DLL_XFORM_DQS11 */ - u_int32_t emc_dll_xform_dqs11; + uint32_t emc_dll_xform_dqs11; /* Specifies the value for EMC_DLL_XFORM_DQS12 */ - u_int32_t emc_dll_xform_dqs12; + uint32_t emc_dll_xform_dqs12; /* Specifies the value for EMC_DLL_XFORM_DQS13 */ - u_int32_t emc_dll_xform_dqs13; + uint32_t emc_dll_xform_dqs13; /* Specifies the value for EMC_DLL_XFORM_DQS14 */ - u_int32_t emc_dll_xform_dqs14; + uint32_t emc_dll_xform_dqs14; /* Specifies the value for EMC_DLL_XFORM_DQS15 */ - u_int32_t emc_dll_xform_dqs15; + uint32_t emc_dll_xform_dqs15; /* Specifies the value for EMC_DLL_XFORM_QUSE0 */ - u_int32_t emc_dll_xform_quse0; + uint32_t emc_dll_xform_quse0; /* Specifies the value for EMC_DLL_XFORM_QUSE1 */ - u_int32_t emc_dll_xform_quse1; + uint32_t emc_dll_xform_quse1; /* Specifies the value for EMC_DLL_XFORM_QUSE2 */ - u_int32_t emc_dll_xform_quse2; + uint32_t emc_dll_xform_quse2; /* Specifies the value for EMC_DLL_XFORM_QUSE3 */ - u_int32_t emc_dll_xform_quse3; + uint32_t emc_dll_xform_quse3; /* Specifies the value for EMC_DLL_XFORM_QUSE4 */ - u_int32_t emc_dll_xform_quse4; + uint32_t emc_dll_xform_quse4; /* Specifies the value for EMC_DLL_XFORM_QUSE5 */ - u_int32_t emc_dll_xform_quse5; + uint32_t emc_dll_xform_quse5; /* Specifies the value for EMC_DLL_XFORM_QUSE6 */ - u_int32_t emc_dll_xform_quse6; + uint32_t emc_dll_xform_quse6; /* Specifies the value for EMC_DLL_XFORM_QUSE7 */ - u_int32_t emc_dll_xform_quse7; + uint32_t emc_dll_xform_quse7; /* Specifies the value for EMC_DLL_XFORM_ADDR0 */ - u_int32_t emc_dll_xform_addr0; + uint32_t emc_dll_xform_addr0; /* Specifies the value for EMC_DLL_XFORM_ADDR1 */ - u_int32_t emc_dll_xform_addr1; + uint32_t emc_dll_xform_addr1; /* Specifies the value for EMC_DLL_XFORM_ADDR2 */ - u_int32_t emc_dll_xform_addr2; + uint32_t emc_dll_xform_addr2; /* Specifies the value for EMC_DLL_XFORM_ADDR3 */ - u_int32_t emc_dll_xform_addr3; + uint32_t emc_dll_xform_addr3; /* Specifies the value for EMC_DLL_XFORM_ADDR4 */ - u_int32_t emc_dll_xform_addr4; + uint32_t emc_dll_xform_addr4; /* Specifies the value for EMC_DLL_XFORM_ADDR5 */ - u_int32_t emc_dll_xform_addr5; + uint32_t emc_dll_xform_addr5; /* Specifies the value for EMC_DLL_XFORM_QUSE8 */ - u_int32_t emc_dll_xform_quse8; + uint32_t emc_dll_xform_quse8; /* Specifies the value for EMC_DLL_XFORM_QUSE9 */ - u_int32_t emc_dll_xform_quse9; + uint32_t emc_dll_xform_quse9; /* Specifies the value for EMC_DLL_XFORM_QUSE10 */ - u_int32_t emc_dll_xform_quse10; + uint32_t emc_dll_xform_quse10; /* Specifies the value for EMC_DLL_XFORM_QUSE11 */ - u_int32_t emc_dll_xform_quse11; + uint32_t emc_dll_xform_quse11; /* Specifies the value for EMC_DLL_XFORM_QUSE12 */ - u_int32_t emc_dll_xform_quse12; + uint32_t emc_dll_xform_quse12; /* Specifies the value for EMC_DLL_XFORM_QUSE13 */ - u_int32_t emc_dll_xform_quse13; + uint32_t emc_dll_xform_quse13; /* Specifies the value for EMC_DLL_XFORM_QUSE14 */ - u_int32_t emc_dll_xform_quse14; + uint32_t emc_dll_xform_quse14; /* Specifies the value for EMC_DLL_XFORM_QUSE15 */ - u_int32_t emc_dll_xform_quse15; + uint32_t emc_dll_xform_quse15; /* Specifies the value for EMC_DLI_TRIM_TXDQS0 */ - u_int32_t emc_dli_trim_tx_dqs0; + uint32_t emc_dli_trim_tx_dqs0; /* Specifies the value for EMC_DLI_TRIM_TXDQS1 */ - u_int32_t emc_dli_trim_tx_dqs1; + uint32_t emc_dli_trim_tx_dqs1; /* Specifies the value for EMC_DLI_TRIM_TXDQS2 */ - u_int32_t emc_dli_trim_tx_dqs2; + uint32_t emc_dli_trim_tx_dqs2; /* Specifies the value for EMC_DLI_TRIM_TXDQS3 */ - u_int32_t emc_dli_trim_tx_dqs3; + uint32_t emc_dli_trim_tx_dqs3; /* Specifies the value for EMC_DLI_TRIM_TXDQS4 */ - u_int32_t emc_dli_trim_tx_dqs4; + uint32_t emc_dli_trim_tx_dqs4; /* Specifies the value for EMC_DLI_TRIM_TXDQS5 */ - u_int32_t emc_dli_trim_tx_dqs5; + uint32_t emc_dli_trim_tx_dqs5; /* Specifies the value for EMC_DLI_TRIM_TXDQS6 */ - u_int32_t emc_dli_trim_tx_dqs6; + uint32_t emc_dli_trim_tx_dqs6; /* Specifies the value for EMC_DLI_TRIM_TXDQS7 */ - u_int32_t emc_dli_trim_tx_dqs7; + uint32_t emc_dli_trim_tx_dqs7; /* Specifies the value for EMC_DLI_TRIM_TXDQS8 */ - u_int32_t emc_dli_trim_tx_dqs8; + uint32_t emc_dli_trim_tx_dqs8; /* Specifies the value for EMC_DLI_TRIM_TXDQS9 */ - u_int32_t emc_dli_trim_tx_dqs9; + uint32_t emc_dli_trim_tx_dqs9; /* Specifies the value for EMC_DLI_TRIM_TXDQS10 */ - u_int32_t emc_dli_trim_tx_dqs10; + uint32_t emc_dli_trim_tx_dqs10; /* Specifies the value for EMC_DLI_TRIM_TXDQS11 */ - u_int32_t emc_dli_trim_tx_dqs11; + uint32_t emc_dli_trim_tx_dqs11; /* Specifies the value for EMC_DLI_TRIM_TXDQS12 */ - u_int32_t emc_dli_trim_tx_dqs12; + uint32_t emc_dli_trim_tx_dqs12; /* Specifies the value for EMC_DLI_TRIM_TXDQS13 */ - u_int32_t emc_dli_trim_tx_dqs13; + uint32_t emc_dli_trim_tx_dqs13; /* Specifies the value for EMC_DLI_TRIM_TXDQS14 */ - u_int32_t emc_dli_trim_tx_dqs14; + uint32_t emc_dli_trim_tx_dqs14; /* Specifies the value for EMC_DLI_TRIM_TXDQS15 */ - u_int32_t emc_dli_trim_tx_dqs15; + uint32_t emc_dli_trim_tx_dqs15; /* Specifies the value for EMC_DLL_XFORM_DQ0 */ - u_int32_t emc_dll_xform_dq0; + uint32_t emc_dll_xform_dq0; /* Specifies the value for EMC_DLL_XFORM_DQ1 */ - u_int32_t emc_dll_xform_dq1; + uint32_t emc_dll_xform_dq1; /* Specifies the value for EMC_DLL_XFORM_DQ2 */ - u_int32_t emc_dll_xform_dq2; + uint32_t emc_dll_xform_dq2; /* Specifies the value for EMC_DLL_XFORM_DQ3 */ - u_int32_t emc_dll_xform_dq3; + uint32_t emc_dll_xform_dq3; /* Specifies the value for EMC_DLL_XFORM_DQ4 */ - u_int32_t emc_dll_xform_dq4; + uint32_t emc_dll_xform_dq4; /* Specifies the value for EMC_DLL_XFORM_DQ5 */ - u_int32_t emc_dll_xform_dq5; + uint32_t emc_dll_xform_dq5; /* Specifies the value for EMC_DLL_XFORM_DQ6 */ - u_int32_t emc_dll_xform_dq6; + uint32_t emc_dll_xform_dq6; /* Specifies the value for EMC_DLL_XFORM_DQ7 */ - u_int32_t emc_dll_xform_dq7; + uint32_t emc_dll_xform_dq7; /* * Specifies the delay after asserting CKE pin during a WarmBoot0 * sequence (in microseconds) */ - u_int32_t warm_boot_wait; + uint32_t warm_boot_wait; /* Specifies the value for EMC_CTT_TERM_CTRL */ - u_int32_t emc_ctt_term_ctrl; + uint32_t emc_ctt_term_ctrl; /* Specifies the value for EMC_ODT_WRITE */ - u_int32_t emc_odt_write; + uint32_t emc_odt_write; /* Specifies the value for EMC_ODT_WRITE */ - u_int32_t emc_odt_read; + uint32_t emc_odt_read; /* Periodic ZQ calibration */ @@ -500,302 +500,302 @@ typedef struct nvboot_sdram_params_rec { * Specifies the value for EMC_ZCAL_INTERVAL * Value 0 disables ZQ calibration */ - u_int32_t emc_zcal_interval; + uint32_t emc_zcal_interval; /* Specifies the value for EMC_ZCAL_WAIT_CNT */ - u_int32_t emc_zcal_wait_cnt; + uint32_t emc_zcal_wait_cnt; /* Specifies the value for EMC_ZCAL_MRW_CMD */ - u_int32_t emc_zcal_mrw_cmd; + uint32_t emc_zcal_mrw_cmd; /* DRAM initialization sequence flow control */ /* Specifies the MRS command value for resetting DLL */ - u_int32_t emc_mrs_reset_dll; + uint32_t emc_mrs_reset_dll; /* Specifies the command for ZQ initialization of device 0 */ - u_int32_t emc_zcal_init_dev0; + uint32_t emc_zcal_init_dev0; /* Specifies the command for ZQ initialization of device 1 */ - u_int32_t emc_zcal_init_dev1; + uint32_t emc_zcal_init_dev1; /* * Specifies the wait time after programming a ZQ initialization * command (in microseconds) */ - u_int32_t emc_zcal_init_wait; + uint32_t emc_zcal_init_wait; /* * Specifies the enable for ZQ calibration at cold boot [bit 0] * and warm boot [bit 1] */ - u_int32_t emc_zcal_warm_cold_boot_enables; + uint32_t emc_zcal_warm_cold_boot_enables; /* * Specifies the MRW command to LPDDR2 for ZQ calibration * on warmboot */ /* Is issued to both devices separately */ - u_int32_t emc_mrw_lpddr2zcal_warm_boot; + uint32_t emc_mrw_lpddr2zcal_warm_boot; /* * Specifies the ZQ command to DDR3 for ZQ calibration on warmboot * Is issued to both devices separately */ - u_int32_t emc_zqcal_ddr3_warm_boot; + uint32_t emc_zqcal_ddr3_warm_boot; /* * Specifies the wait time for ZQ calibration on warmboot * (in microseconds) */ - u_int32_t emc_zcal_warm_boot_wait; + uint32_t emc_zcal_warm_boot_wait; /* * Specifies the enable for DRAM Mode Register programming * at warm boot */ - u_int32_t emc_mrs_warm_boot_enable; + uint32_t emc_mrs_warm_boot_enable; /* * Specifies the wait time after sending an MRS DLL reset command * in microseconds) */ - u_int32_t emc_mrs_reset_dll_wait; + uint32_t emc_mrs_reset_dll_wait; /* Specifies the extra MRS command to initialize mode registers */ - u_int32_t emc_mrs_extra; + uint32_t emc_mrs_extra; /* Specifies the extra MRS command at warm boot */ - u_int32_t emc_warm_boot_mrs_extra; + uint32_t emc_warm_boot_mrs_extra; /* Specifies the EMRS command to enable the DDR2 DLL */ - u_int32_t emc_emrs_ddr2_dll_enable; + uint32_t emc_emrs_ddr2_dll_enable; /* Specifies the MRS command to reset the DDR2 DLL */ - u_int32_t emc_mrs_ddr2_dll_reset; + uint32_t emc_mrs_ddr2_dll_reset; /* Specifies the EMRS command to set OCD calibration */ - u_int32_t emc_emrs_ddr2_ocd_calib; + uint32_t emc_emrs_ddr2_ocd_calib; /* * Specifies the wait between initializing DDR and setting OCD * calibration (in microseconds) */ - u_int32_t emc_ddr2_wait; + uint32_t emc_ddr2_wait; /* Specifies the value for EMC_CLKEN_OVERRIDE */ - u_int32_t emc_clken_override; + uint32_t emc_clken_override; /* Specifies the value for MC_DIS_EXTRA_SNAP_LEVELS */ - u_int32_t mc_dis_extra_snap_levels; + uint32_t mc_dis_extra_snap_levels; /* * Specifies LOG2 of the extra refresh numbers after booting * Program 0 to disable */ - u_int32_t emc_extra_refresh_num; + uint32_t emc_extra_refresh_num; /* Specifies the master override for all EMC clocks */ - u_int32_t emc_clken_override_allwarm_boot; + uint32_t emc_clken_override_allwarm_boot; /* Specifies the master override for all MC clocks */ - u_int32_t mc_clken_override_allwarm_boot; + uint32_t mc_clken_override_allwarm_boot; /* Specifies digital dll period, choosing between 4 to 64 ms */ - u_int32_t emc_cfg_dig_dll_period_warm_boot; + uint32_t emc_cfg_dig_dll_period_warm_boot; /* Pad controls */ /* Specifies the value for PMC_VDDP_SEL */ - u_int32_t pmc_vddp_sel; + uint32_t pmc_vddp_sel; /* Specifies the wait time after programming PMC_VDDP_SEL */ - u_int32_t pmc_vddp_sel_wait; + uint32_t pmc_vddp_sel_wait; /* Specifies the value for PMC_DDR_PWR */ - u_int32_t pmc_ddr_pwr; + uint32_t pmc_ddr_pwr; /* Specifies the value for PMC_DDR_CFG */ - u_int32_t pmc_ddr_cfg; + uint32_t pmc_ddr_cfg; /* Specifies the value for PMC_IO_DPD3_REQ */ - u_int32_t pmc_io_dpd3_req; + uint32_t pmc_io_dpd3_req; /* Specifies the wait time after programming PMC_IO_DPD3_REQ */ - u_int32_t pmc_io_dpd3_req_wait; + uint32_t pmc_io_dpd3_req_wait; /* Specifies the value for PMC_REG_SHORT */ - u_int32_t pmc_reg_short; + uint32_t pmc_reg_short; /* Specifies the value for PMC_NO_IOPOWER */ - u_int32_t pmc_no_io_power; + uint32_t pmc_no_io_power; /* Specifies the wait time after programming PMC_POR_DPD_CTRL */ - u_int32_t pmc_por_dpd_ctrl_wait; + uint32_t pmc_por_dpd_ctrl_wait; /* Specifies the value for EMC_XM2CMDPADCTRL */ - u_int32_t emc_xm2cmd_pad_ctrl; + uint32_t emc_xm2cmd_pad_ctrl; /* Specifies the value for EMC_XM2CMDPADCTRL2 */ - u_int32_t emc_xm2cmd_pad_ctrl2; + uint32_t emc_xm2cmd_pad_ctrl2; /* Specifies the value for EMC_XM2CMDPADCTRL3 */ - u_int32_t emc_xm2cmd_pad_ctrl3; + uint32_t emc_xm2cmd_pad_ctrl3; /* Specifies the value for EMC_XM2CMDPADCTRL4 */ - u_int32_t emc_xm2cmd_pad_ctrl4; + uint32_t emc_xm2cmd_pad_ctrl4; /* Specifies the value for EMC_XM2CMDPADCTRL5 */ - u_int32_t emc_xm2cmd_pad_ctrl5; + uint32_t emc_xm2cmd_pad_ctrl5; /* Specifies the value for EMC_XM2DQSPADCTRL */ - u_int32_t emc_xm2dqs_pad_ctrl; + uint32_t emc_xm2dqs_pad_ctrl; /* Specifies the value for EMC_XM2DQSPADCTRL2 */ - u_int32_t emc_xm2dqs_pad_ctrl2; + uint32_t emc_xm2dqs_pad_ctrl2; /* Specifies the value for EMC_XM2DQSPADCTRL3 */ - u_int32_t emc_xm2dqs_pad_ctrl3; + uint32_t emc_xm2dqs_pad_ctrl3; /* Specifies the value for EMC_XM2DQSPADCTRL4 */ - u_int32_t emc_xm2dqs_pad_ctrl4; + uint32_t emc_xm2dqs_pad_ctrl4; /* Specifies the value for EMC_XM2DQSPADCTRL5 */ - u_int32_t emc_xm2dqs_pad_ctrl5; + uint32_t emc_xm2dqs_pad_ctrl5; /* Specifies the value for EMC_XM2DQSPADCTRL6 */ - u_int32_t emc_xm2dqs_pad_ctrl6; + uint32_t emc_xm2dqs_pad_ctrl6; /* Specifies the value for EMC_XM2DQPADCTRL */ - u_int32_t emc_xm2dq_pad_ctrl; + uint32_t emc_xm2dq_pad_ctrl; /* Specifies the value for EMC_XM2DQPADCTRL2 */ - u_int32_t emc_xm2dq_pad_ctrl2; + uint32_t emc_xm2dq_pad_ctrl2; /* Specifies the value for EMC_XM2DQPADCTRL3 */ - u_int32_t emc_xm2dq_pad_ctrl3; + uint32_t emc_xm2dq_pad_ctrl3; /* Specifies the value for EMC_XM2CLKPADCTRL */ - u_int32_t emc_xm2clk_pad_ctrl; + uint32_t emc_xm2clk_pad_ctrl; /* Specifies the value for EMC_XM2CLKPADCTRL2 */ - u_int32_t emc_xm2clk_pad_ctrl2; + uint32_t emc_xm2clk_pad_ctrl2; /* Specifies the value for EMC_XM2COMPPADCTRL */ - u_int32_t emc_xm2comp_pad_ctrl; + uint32_t emc_xm2comp_pad_ctrl; /* Specifies the value for EMC_XM2VTTGENPADCTRL */ - u_int32_t emc_xm2vttgen_pad_ctrl; + uint32_t emc_xm2vttgen_pad_ctrl; /* Specifies the value for EMC_XM2VTTGENPADCTRL2 */ - u_int32_t emc_xm2vttgen_pad_ctrl2; + uint32_t emc_xm2vttgen_pad_ctrl2; /* Specifies the value for EMC_XM2VTTGENPADCTRL3 */ - u_int32_t emc_xm2vttgen_pad_ctrl3; + uint32_t emc_xm2vttgen_pad_ctrl3; /* Specifies the value for EMC_ACPD_CONTROL */ - u_int32_t emc_acpd_control; + uint32_t emc_acpd_control; /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE_CFG */ - u_int32_t emc_swizzle_rank0_byte_cfg; + uint32_t emc_swizzle_rank0_byte_cfg; /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE0 */ - u_int32_t emc_swizzle_rank0_byte0; + uint32_t emc_swizzle_rank0_byte0; /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE1 */ - u_int32_t emc_swizzle_rank0_byte1; + uint32_t emc_swizzle_rank0_byte1; /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE2 */ - u_int32_t emc_swizzle_rank0_byte2; + uint32_t emc_swizzle_rank0_byte2; /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE3 */ - u_int32_t emc_swizzle_rank0_byte3; + uint32_t emc_swizzle_rank0_byte3; /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE_CFG */ - u_int32_t emc_swizzle_rank1_byte_cfg; + uint32_t emc_swizzle_rank1_byte_cfg; /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE0 */ - u_int32_t emc_swizzle_rank1_byte0; + uint32_t emc_swizzle_rank1_byte0; /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE1 */ - u_int32_t emc_swizzle_rank1_byte1; + uint32_t emc_swizzle_rank1_byte1; /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE2 */ - u_int32_t emc_swizzle_rank1_byte2; + uint32_t emc_swizzle_rank1_byte2; /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE3 */ - u_int32_t emc_swizzle_rank1_byte3; + uint32_t emc_swizzle_rank1_byte3; /* Specifies the value for EMC_DSR_VTTGEN_DRV */ - u_int32_t emc_dsr_vttgen_drv; + uint32_t emc_dsr_vttgen_drv; /* Specifies the value for EMC_TXDSRVTTGEN */ - u_int32_t emc_txdsrvttgen; + uint32_t emc_txdsrvttgen; /* Specifies the value for EMC_BGBIAS_CTL */ - u_int32_t emc_bgbias_ctl0; + uint32_t emc_bgbias_ctl0; /* DRAM size information */ /* Specifies the value for MC_EMEM_ADR_CFG */ - u_int32_t mc_emem_adr_cfg; + uint32_t mc_emem_adr_cfg; /* Specifies the value for MC_EMEM_ADR_CFG_DEV0 */ - u_int32_t mc_emem_adr_cfg_dev0; + uint32_t mc_emem_adr_cfg_dev0; /* Specifies the value for MC_EMEM_ADR_CFG_DEV1 */ - u_int32_t mc_emem_adr_cfg_dev1; + uint32_t mc_emem_adr_cfg_dev1; /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG0 */ - u_int32_t mc_emem_adr_cfg_bank_mask0; + uint32_t mc_emem_adr_cfg_bank_mask0; /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG1 */ - u_int32_t mc_emem_adr_cfg_bank_mask1; + uint32_t mc_emem_adr_cfg_bank_mask1; /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG2 */ - u_int32_t mc_emem_adr_cfg_bank_mask2; + uint32_t mc_emem_adr_cfg_bank_mask2; /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG3 */ - u_int32_t mc_emem_adr_cfg_bank_swizzle3; + uint32_t mc_emem_adr_cfg_bank_swizzle3; /* * Specifies the value for MC_EMEM_CFG which holds the external memory * size (in KBytes) */ - u_int32_t mc_emem_cfg; + uint32_t mc_emem_cfg; /* MC arbitration configuration */ /* Specifies the value for MC_EMEM_ARB_CFG */ - u_int32_t mc_emem_arb_cfg; + uint32_t mc_emem_arb_cfg; /* Specifies the value for MC_EMEM_ARB_OUTSTANDING_REQ */ - u_int32_t mc_emem_arb_outstanding_req; + uint32_t mc_emem_arb_outstanding_req; /* Specifies the value for MC_EMEM_ARB_TIMING_RCD */ - u_int32_t mc_emem_arb_timing_rcd; + uint32_t mc_emem_arb_timing_rcd; /* Specifies the value for MC_EMEM_ARB_TIMING_RP */ - u_int32_t mc_emem_arb_timing_rp; + uint32_t mc_emem_arb_timing_rp; /* Specifies the value for MC_EMEM_ARB_TIMING_RC */ - u_int32_t mc_emem_arb_timing_rc; + uint32_t mc_emem_arb_timing_rc; /* Specifies the value for MC_EMEM_ARB_TIMING_RAS */ - u_int32_t mc_emem_arb_timing_ras; + uint32_t mc_emem_arb_timing_ras; /* Specifies the value for MC_EMEM_ARB_TIMING_FAW */ - u_int32_t mc_emem_arb_timing_faw; + uint32_t mc_emem_arb_timing_faw; /* Specifies the value for MC_EMEM_ARB_TIMING_RRD */ - u_int32_t mc_emem_arb_timing_rrd; + uint32_t mc_emem_arb_timing_rrd; /* Specifies the value for MC_EMEM_ARB_TIMING_RAP2PRE */ - u_int32_t mc_emem_arb_timing_rap2pre; + uint32_t mc_emem_arb_timing_rap2pre; /* Specifies the value for MC_EMEM_ARB_TIMING_WAP2PRE */ - u_int32_t mc_emem_arb_timing_wap2pre; + uint32_t mc_emem_arb_timing_wap2pre; /* Specifies the value for MC_EMEM_ARB_TIMING_R2R */ - u_int32_t mc_emem_arb_timing_r2r; + uint32_t mc_emem_arb_timing_r2r; /* Specifies the value for MC_EMEM_ARB_TIMING_W2W */ - u_int32_t mc_emem_arb_timing_w2w; + uint32_t mc_emem_arb_timing_w2w; /* Specifies the value for MC_EMEM_ARB_TIMING_R2W */ - u_int32_t mc_emem_arb_timing_r2w; + uint32_t mc_emem_arb_timing_r2w; /* Specifies the value for MC_EMEM_ARB_TIMING_W2R */ - u_int32_t mc_emem_arb_timing_w2r; + uint32_t mc_emem_arb_timing_w2r; /* Specifies the value for MC_EMEM_ARB_DA_TURNS */ - u_int32_t mc_emem_arb_da_turns; + uint32_t mc_emem_arb_da_turns; /* Specifies the value for MC_EMEM_ARB_DA_COVERS */ - u_int32_t mc_emem_arb_da_covers; + uint32_t mc_emem_arb_da_covers; /* Specifies the value for MC_EMEM_ARB_MISC0 */ - u_int32_t mc_emem_arb_misc0; + uint32_t mc_emem_arb_misc0; /* Specifies the value for MC_EMEM_ARB_MISC1 */ - u_int32_t mc_emem_arb_misc1; + uint32_t mc_emem_arb_misc1; /* Specifies the value for MC_EMEM_ARB_RING1_THROTTLE */ - u_int32_t mc_emem_arb_ring1_throttle; + uint32_t mc_emem_arb_ring1_throttle; /* Specifies the value for MC_EMEM_ARB_OVERRIDE */ - u_int32_t mc_emem_arb_override; + uint32_t mc_emem_arb_override; /* Specifies the value for MC_EMEM_ARB_OVERRIDE_1 */ - u_int32_t mc_emem_arb_override1; + uint32_t mc_emem_arb_override1; /* Specifies the value for MC_EMEM_ARB_RSV */ - u_int32_t mc_emem_arb_rsv; + uint32_t mc_emem_arb_rsv; /* Specifies the value for MC_CLKEN_OVERRIDE */ - u_int32_t mc_clken_override; + uint32_t mc_clken_override; /* Specifies the value for MC_STAT_CONTROL */ - u_int32_t mc_stat_control; + uint32_t mc_stat_control; /* Specifies the value for MC_DISPLAY_SNAP_RING */ - u_int32_t mc_display_snap_ring; + uint32_t mc_display_snap_ring; /* Specifies the value for MC_VIDEO_PROTECT_BOM */ - u_int32_t mc_video_protect_bom; + uint32_t mc_video_protect_bom; /* Specifies the value for MC_VIDEO_PROTECT_BOM_ADR_HI */ - u_int32_t mc_video_protect_bom_adr_hi; + uint32_t mc_video_protect_bom_adr_hi; /* Specifies the value for MC_VIDEO_PROTECT_SIZE_MB */ - u_int32_t mc_video_protect_size_mb; + uint32_t mc_video_protect_size_mb; /* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE */ - u_int32_t mc_video_protect_vpr_override; + uint32_t mc_video_protect_vpr_override; /* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE1 */ - u_int32_t mc_video_protect_vpr_override1; + uint32_t mc_video_protect_vpr_override1; /* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_0 */ - u_int32_t mc_video_protect_gpu_override0; + uint32_t mc_video_protect_gpu_override0; /* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_1 */ - u_int32_t mc_video_protect_gpu_override1; + uint32_t mc_video_protect_gpu_override1; /* Specifies the value for MC_SEC_CARVEOUT_BOM */ - u_int32_t mc_sec_carveout_bom; + uint32_t mc_sec_carveout_bom; /* Specifies the value for MC_SEC_CARVEOUT_ADR_HI */ - u_int32_t mc_sec_carveout_adr_hi; + uint32_t mc_sec_carveout_adr_hi; /* Specifies the value for MC_SEC_CARVEOUT_SIZE_MB */ - u_int32_t mc_sec_carveout_size_mb; + uint32_t mc_sec_carveout_size_mb; /* Specifies the value for MC_VIDEO_PROTECT_REG_CTRL.VIDEO_PROTECT_WRITE_ACCESS */ - u_int32_t mc_video_protect_write_access; + uint32_t mc_video_protect_write_access; /* Specifies the value for MC_SEC_CARVEOUT_REG_CTRL.SEC_CARVEOUT_WRITE_ACCESS */ - u_int32_t mc_sec_carveout_protect_write_access; + uint32_t mc_sec_carveout_protect_write_access; /* Specifies enable for CA training */ - u_int32_t emc_ca_training_enable; + uint32_t emc_ca_training_enable; /* Specifies the value for EMC_CA_TRAINING_TIMING_CNTRL1 */ - u_int32_t emc_ca_training_timing_cntl1; + uint32_t emc_ca_training_timing_cntl1; /* Specifies the value for EMC_CA_TRAINING_TIMING_CNTRL2 */ - u_int32_t emc_ca_training_timing_cntl2; + uint32_t emc_ca_training_timing_cntl2; /* Set if bit 6 select is greater than bit 7 select; uses aremc.spec packet SWIZZLE_BIT6_GT_BIT7 */ - u_int32_t swizzle_rank_byte_encode; + uint32_t swizzle_rank_byte_encode; /* Specifies enable and offset for patched boot rom write */ - u_int32_t boot_rom_patch_control; + uint32_t boot_rom_patch_control; /* Specifies data for patched boot rom write */ - u_int32_t boot_rom_patch_data; + uint32_t boot_rom_patch_data; /* Specifies the value for MC_MTS_CARVEOUT_BOM */ - u_int32_t mc_mts_carveout_bom; + uint32_t mc_mts_carveout_bom; /* Specifies the value for MC_MTS_CARVEOUT_ADR_HI */ - u_int32_t mc_mts_carveout_adr_hi; + uint32_t mc_mts_carveout_adr_hi; /* Specifies the value for MC_MTS_CARVEOUT_SIZE_MB */ - u_int32_t mc_mts_carveout_size_mb; + uint32_t mc_mts_carveout_size_mb; /* Specifies the value for MC_MTS_CARVEOUT_REG_CTRL */ - u_int32_t mc_mts_carveout_reg_ctrl; + uint32_t mc_mts_carveout_reg_ctrl; /* End of generated code by warmboot_code_gen */ } nvboot_sdram_params; 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