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authorStephen Warren <swarren@nvidia.com>2014-10-14 10:25:07 -0600
committerStephen Warren <swarren@nvidia.com>2014-10-14 11:07:35 -0600
commit7e87c2f40320afe13041db884729fae46f0a8f44 (patch)
tree543158c1a53d3288e65f3a76beae90b3bb961f53
parent7b45d2cf33f27c1091f1a17e3b4be4017ffe0761 (diff)
downloadtegra-pinmux-scripts-7e87c2f40320afe13041db884729fae46f0a8f44.tar.gz
Board CSV import: Support all Tegra124 OD pins
Complete the list of OD pins in the CSV -> *.board import script for Tegra124. Signed-off-by: Stephen Warren <swarren@nvidia.com>
-rwxr-xr-xcsv-to-board-tegra124-xlsx.py3
1 files changed, 1 insertions, 2 deletions
diff --git a/csv-to-board-tegra124-xlsx.py b/csv-to-board-tegra124-xlsx.py
index be985c2..c150ffa 100755
--- a/csv-to-board-tegra124-xlsx.py
+++ b/csv-to-board-tegra124-xlsx.py
@@ -219,9 +219,8 @@ with open(csvfile, newline='') as fh:
print('ERROR: %s: MUX CSV %s not in SOC F0..3 %s' % (ball_name, mux, repr(gpio_pin.funcs)), file=sys.stderr)
sys.exit(1)
- if ball_name.startswith('ddc_'):
+ if ball_name in ('reset_out_n', 'owr', 'hdmi_int', 'ddc_scl', 'ddc_sda'):
# These balls' pad type is always OD, so we don't need to set it
- # FIXME: There are a few other OD type pads to check for
# FIXME: The SoC data structure should tell us the pad type instead of hard-coding it
od = False