Support Tegra210

Tegra210 changes the pinmux HW in a few ways; at least:

- The set of drive groups is much more 1:1 with the set of pins. Most
  pins have an associated drive group register as well as an associated
  pinmux register, and most drive groups cover a single pin.
- Some register fields have moved from the drive group registers into
  the pinmux registers.
- The set of available options for each pin and group varies relative to
  previous chips, and hence the register layouts vary a bit too.

This patch updates tegra-pinmux-scripts minimally to handle these
changes, to a level equivalent to the support for previous chips. For
example, some new options such as per-pin schmitt aren't handled since
the syseng-supplied pinmux spreadsheets don't provide a value for this
option.

csv-to-board-tegra124-xlsx.py is renamed to csv-to-board.py since it now
supports boards using different SoCs, and it's not worth encoding all
supported SoCs in the filename (Tegra30/114 aren't supported by it, hence
the previous naming).

Signed-off-by: Stephen Warren <swarren@nvidia.com>

1 files changed, 3 insertions, 1 deletions

diff --git a/board-to-kernel-dt.py b/board-to-kernel-dt.py
index 20f27c3..394b4ac 100755
--- a/board-to-kernel-dt.py
+++ b/board-to-kernel-dt.py
@@ -56,8 +56,10 @@ for pincfg in board.pincfgs_by_num():
     print('				nvidia,enable-input = <' + mapper_bool(pincfg.e_inp) + '>;')
     if pincfg.gpio_pin.od:
         print('				nvidia,open-drain = <' + mapper_bool(pincfg.od) + '>;')
-    if hasattr(pincfg.gpio_pin, 'rcv_sel') and pincfg.gpio_pin.rcv_sel:
+    if board.soc.soc_pins_have_rcv_sel and pincfg.gpio_pin.rcv_sel and hasattr(pincfg.gpio_pin, 'rcv_sel'):
         print('				nvidia,rcv-sel = <' + mapper_bool(pincfg.rcv_sel) + '>;')
+    if board.soc.soc_pins_have_e_io_hv and pincfg.gpio_pin.e_io_hv and hasattr(pincfg.gpio_pin, 'e_io_hv'):
+        print('				nvidia,io-hv = <' + mapper_bool(pincfg.e_io_hv) + '>;')
     print('			};')
 
 # FIXME: Handle drive groups