Support Tegra210

Tegra210 changes the pinmux HW in a few ways; at least:

- The set of drive groups is much more 1:1 with the set of pins. Most
  pins have an associated drive group register as well as an associated
  pinmux register, and most drive groups cover a single pin.
- Some register fields have moved from the drive group registers into
  the pinmux registers.
- The set of available options for each pin and group varies relative to
  previous chips, and hence the register layouts vary a bit too.

This patch updates tegra-pinmux-scripts minimally to handle these
changes, to a level equivalent to the support for previous chips. For
example, some new options such as per-pin schmitt aren't handled since
the syseng-supplied pinmux spreadsheets don't provide a value for this
option.

csv-to-board-tegra124-xlsx.py is renamed to csv-to-board.py since it now
supports boards using different SoCs, and it's not worth encoding all
supported SoCs in the filename (Tegra30/114 aren't supported by it, hence
the previous naming).

Signed-off-by: Stephen Warren <swarren@nvidia.com>

1 files changed, 53 insertions, 13 deletions

diff --git a/board-to-uboot.py b/board-to-uboot.py
index c679191..f47f6f6 100755
--- a/board-to-uboot.py
+++ b/board-to-uboot.py
@@ -80,17 +80,48 @@ dump_c_table(headings, 'GPIO_INIT', gpio_table)
 print('''\
 };
 
-#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel)	\\
-	{							\\
-		.pingrp		= PMUX_PINGRP_##_pingrp,	\\
-		.func		= PMUX_FUNC_##_mux,		\\
-		.pull		= PMUX_PULL_##_pull,		\\
-		.tristate	= PMUX_TRI_##_tri,		\\
-		.io		= PMUX_PIN_##_io,		\\
-		.od		= PMUX_PIN_OD_##_od,		\\
-		.rcv_sel	= PMUX_PIN_RCV_SEL_##_rcv_sel,	\\
-		.lock		= PMUX_PIN_LOCK_DEFAULT,	\\
-		.ioreset	= PMUX_PIN_IO_RESET_DEFAULT,	\\
+''', end='')
+
+params = ['_pingrp', '_mux', '_pull', '_tri', '_io', '_od']
+if board.soc.soc_pins_have_rcv_sel:
+    params += ['_rcv_sel',]
+if board.soc.soc_pins_have_e_io_hv:
+    params += ['_e_io_hv',]
+s = gen_wrapped_c_macro_header('PINCFG', params)
+
+s += '''\
+	{
+		.pingrp		= PMUX_PINGRP_##_pingrp,
+		.func		= PMUX_FUNC_##_mux,
+		.pull		= PMUX_PULL_##_pull,
+		.tristate	= PMUX_TRI_##_tri,
+		.io		= PMUX_PIN_##_io,
+		.od		= PMUX_PIN_OD_##_od,
+'''
+
+if board.soc.soc_pins_have_rcv_sel:
+	s += '''\
+		.rcv_sel	= PMUX_PIN_RCV_SEL_##_rcv_sel,
+'''
+
+if board.soc.soc_pins_have_e_io_hv:
+	s += '''\
+		.e_io_hv	= PMUX_PIN_E_IO_HV_##_e_io_hv,
+'''
+
+s += '''\
+		.lock		= PMUX_PIN_LOCK_DEFAULT,
+'''
+
+if board.soc.soc_pins_have_ior:
+	s += '''\
+		.ioreset	= PMUX_PIN_IO_RESET_DEFAULT,
+'''
+
+s = append_aligned_tabs_indent_with_tabs(s)
+print(s)
+
+print('''\
 	}
 
 static const struct pmux_pingrp_config %(board_varname)s_pingrps[] = {
@@ -125,6 +156,11 @@ def mapper_rcv_sel(gpio_pin, val):
         return 'DEFAULT'
     return {False: 'NORMAL', True: 'HIGH'}[val]
 
+def mapper_e_io_hv(gpio_pin, val):
+    if not gpio_pin.e_io_hv:
+        return 'DEFAULT'
+    return {False: 'NORMAL', True: 'HIGH'}[val]
+
 pincfg_table = []
 for pincfg in board.pincfgs_by_num():
     row = (
@@ -135,12 +171,16 @@ for pincfg in board.pincfgs_by_num():
         mapper_e_input(pincfg.e_inp),
         mapper_od(pincfg.gpio_pin, pincfg.od),
     )
-    if board.soc.has_rcv_sel:
+    if board.soc.soc_pins_have_rcv_sel:
         row += (mapper_rcv_sel(pincfg.gpio_pin, pincfg.rcv_sel),)
+    if board.soc.soc_pins_have_e_io_hv:
+        row += (mapper_e_io_hv(pincfg.gpio_pin, pincfg.e_io_hv),)
     pincfg_table.append(row)
 headings = ('pingrp', 'mux', 'pull', 'tri', 'e_input', 'od')
-if board.soc.has_rcv_sel:
+if board.soc.soc_pins_have_rcv_sel:
     headings += ('rcv_sel',)
+if board.soc.soc_pins_have_e_io_hv:
+    headings += ('e_io_hv',)
 dump_c_table(headings, 'PINCFG', pincfg_table)
 
 print('''\