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authorStephen Warren <swarren@nvidia.com>2015-03-24 16:45:30 -0600
committerStephen Warren <swarren@nvidia.com>2016-04-21 15:54:22 -0600
commitac1d5375c3c72c3647eff07e776a31b493a8abff (patch)
tree8cfb0b258ec2cf5a6e59a7762d3450ebd8536e59 /configs/jetson-tk1.board
parentdde73ef3b7996d9687b829ada97a201db5712efa (diff)
downloadtegra-pinmux-scripts-ac1d5375c3c72c3647eff07e776a31b493a8abff.tar.gz
Import latest Jetson TK1 spreadsheet
This imports v11 of "Jetson TK1 Development Platform Pin Mux" from https://developer.nvidia.com/embedded/downloads. The new version defines the mux option for the MIPI pad ctrl selection. The OWR pin no longer has an entry in the configuration table because the only mux option it support is OWR, that feature isn't supported, and hence can't conflict with any other pin. This pin can only usefully be used as a GPIO. Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'configs/jetson-tk1.board')
-rw-r--r--configs/jetson-tk1.board6
1 files changed, 5 insertions, 1 deletions
diff --git a/configs/jetson-tk1.board b/configs/jetson-tk1.board
index 9b029df..57d0593 100644
--- a/configs/jetson-tk1.board
+++ b/configs/jetson-tk1.board
@@ -182,7 +182,6 @@ pins = (
('uart3_rts_n_pc0', 'gmi', None, 'down', True, False, False, False),
('uart3_rxd_pw7', 'rsvd2', None, 'down', True, False, False, False),
('uart3_txd_pw6', 'rsvd2', None, 'down', True, False, False, False),
- ('owr', 'rsvd2', None, 'down', True, False, False, False),
('hdmi_cec_pee3', 'cec', None, 'none', False, True, False, False),
('hdmi_int_pn7', None, 'in', 'down', True, True, False, False),
('ddc_scl_pv4', 'i2c4', None, 'none', False, True, False, False),
@@ -196,3 +195,8 @@ pins = (
drive_groups = (
)
+
+mipi_pad_ctrl_groups = (
+ #pin, mux
+ ('dsi_b', 'dsi_b'),
+)