diff options
| author | Sowjanya Komatineni <skomatineni@nvidia.com> | 2019-06-20 19:00:55 +0200 |
|---|---|---|
| committer | Stephen Warren <swarren@nvidia.com> | 2019-07-01 17:42:06 -0600 |
| commit | bae95bd85e02fdfda4ff1fa0bcdac9793ad3120c (patch) | |
| tree | 3f8640c819a934fe5a0eb141233060a6de640343 /configs/tegra124.soc | |
| parent | 51bcefec10d769b440125ad050a9865efc57b1e7 (diff) | |
| download | tegra-pinmux-scripts-master.tar.gz | |
Parked bits for SDMMC2 and SDMMC4 are part of CFGPAD register rather
than pinmux registers and contains bit for each of their pins.
So updating pinctrl Tegra driver to use bitmask for parked
configuration rather than bit.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
[treding@nvidia.com: reshuffle fields to match driver order]
[treding@nvidia.com: use bitmask 0 for unsupported]
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'configs/tegra124.soc')
| -rw-r--r-- | configs/tegra124.soc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/configs/tegra124.soc b/configs/tegra124.soc index 1012c7c..e0e2595 100644 --- a/configs/tegra124.soc +++ b/configs/tegra124.soc @@ -13,6 +13,7 @@ soc_drvgroups_have_drvtype = True soc_drvgroups_have_hsm = True soc_drvgroups_have_lpmd = True soc_drvgroups_have_schmitt = True +soc_drvgroups_have_parked = False soc_pins_all_have_od = False soc_pins_all_have_parked = False soc_pins_all_have_schmitt = False |