diff options
| author | Stephen Warren <swarren@nvidia.com> | 2015-02-11 12:25:38 -0700 |
|---|---|---|
| committer | Stephen Warren <swarren@nvidia.com> | 2015-02-25 15:58:04 -0700 |
| commit | ca5bbef466b5c7ba899fbf69078049d6abbcce96 (patch) | |
| tree | 5d4e78dcf01528132bfe73514ba7dec63bd62629 /configs/tegra30.soc | |
| parent | 32ceb32d4f3babf4ad97dbd4d7002ee7a59f32ba (diff) | |
| download | tegra-pinmux-scripts-ca5bbef466b5c7ba899fbf69078049d6abbcce96.tar.gz | |
Support Tegra210
Tegra210 changes the pinmux HW in a few ways; at least:
- The set of drive groups is much more 1:1 with the set of pins. Most
pins have an associated drive group register as well as an associated
pinmux register, and most drive groups cover a single pin.
- Some register fields have moved from the drive group registers into
the pinmux registers.
- The set of available options for each pin and group varies relative to
previous chips, and hence the register layouts vary a bit too.
This patch updates tegra-pinmux-scripts minimally to handle these
changes, to a level equivalent to the support for previous chips. For
example, some new options such as per-pin schmitt aren't handled since
the syseng-supplied pinmux spreadsheets don't provide a value for this
option.
csv-to-board-tegra124-xlsx.py is renamed to csv-to-board.py since it now
supports boards using different SoCs, and it's not worth encoding all
supported SoCs in the filename (Tegra30/114 aren't supported by it, hence
the previous naming).
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'configs/tegra30.soc')
| -rw-r--r-- | configs/tegra30.soc | 21 |
1 files changed, 19 insertions, 2 deletions
diff --git a/configs/tegra30.soc b/configs/tegra30.soc index d91bccd..fd6c6ad 100644 --- a/configs/tegra30.soc +++ b/configs/tegra30.soc @@ -2,8 +2,25 @@ kernel_copyright_years = '2011-2012' kernel_author = 'Stephen Warren <swarren@nvidia.com>' uboot_copyright_years = '2010-2014' -has_rcv_sel = False -has_drvtype = False +soc_has_io_clamping = False +soc_combine_pin_drvgroup = False +soc_rsvd_base = 1 +soc_drvgroups_have_drvtype = False +soc_drvgroups_have_hsm = True +soc_drvgroups_have_lpmd = True +soc_drvgroups_have_schmitt = True +soc_pins_all_have_od = False +soc_pins_all_have_schmitt = False +soc_pins_have_drvtype = False +soc_pins_have_e_io_hv = False +soc_pins_have_hsm = False +soc_pins_have_ior = True +soc_pins_have_od = True +soc_pins_have_rcv_sel = False +soc_pins_have_schmitt = False +soc_drv_reg_base = 0x868 +soc_einput_b = 5 +soc_odrain_b = 6 gpios = ( #name, gpio, reg, f0, f1, f2, f3, od, ior |