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| author | Sowjanya Komatineni <skomatineni@nvidia.com> | 2019-06-20 19:00:55 +0200 |
|---|---|---|
| committer | Stephen Warren <swarren@nvidia.com> | 2019-07-01 17:42:06 -0600 |
| commit | bae95bd85e02fdfda4ff1fa0bcdac9793ad3120c (patch) | |
| tree | 3f8640c819a934fe5a0eb141233060a6de640343 /csv-to-board.py | |
| parent | 51bcefec10d769b440125ad050a9865efc57b1e7 (diff) | |
| download | tegra-pinmux-scripts-master.tar.gz | |
Parked bits for SDMMC2 and SDMMC4 are part of CFGPAD register rather
than pinmux registers and contains bit for each of their pins.
So updating pinctrl Tegra driver to use bitmask for parked
configuration rather than bit.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
[treding@nvidia.com: reshuffle fields to match driver order]
[treding@nvidia.com: use bitmask 0 for unsupported]
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'csv-to-board.py')
0 files changed, 0 insertions, 0 deletions