diff options
| author | Rhyland Klein <rklein@nvidia.com> | 2016-04-07 16:55:37 -0400 |
|---|---|---|
| committer | Stephen Warren <swarren@nvidia.com> | 2016-04-07 15:15:51 -0600 |
| commit | dde73ef3b7996d9687b829ada97a201db5712efa (patch) | |
| tree | 07099dce3c7183db90b309fb565164dc02451d59 /soc-to-kernel-pinctrl-driver.py | |
| parent | 8b60f5dfb9e44904ff19cde1294881d64192d5bc (diff) | |
| download | tegra-pinmux-scripts-dde73ef3b7996d9687b829ada97a201db5712efa.tar.gz | |
soc: Add support for Parked bits for Tegra210
Tegra210 has a parked bit for each pin. Add code to express this by
updating the kernel driver MACROs to add in parked_* fields so that
the kernel can handle them as it sees fit.
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'soc-to-kernel-pinctrl-driver.py')
| -rwxr-xr-x | soc-to-kernel-pinctrl-driver.py | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/soc-to-kernel-pinctrl-driver.py b/soc-to-kernel-pinctrl-driver.py index 46547b1..3f69a46 100755 --- a/soc-to-kernel-pinctrl-driver.py +++ b/soc-to-kernel-pinctrl-driver.py @@ -259,6 +259,17 @@ s += '''\ .rcv_sel_bit = %(rcv_sel_val)s ''' % globals() +if soc.soc_pins_all_have_parked: + s += '''\ + .parked_reg = PINGROUP_REG(r), + .parked_bank = %s, + .parked_bit = %s, +''' % (soc.soc_parked_bank, soc.soc_parked_bit) +else: + s+= '''\ + .parked_reg = -1, +''' + if soc.soc_pins_have_hsm: s += '''\ .hsm_bit = PINGROUP_BIT_##hsm(9), @@ -358,6 +369,7 @@ s += '''\ .rcv_sel_bit = -1, .drv_reg = DRV_PINGROUP_REG(r), .drv_bank = 0, + .parked_reg = -1, .hsm_bit = %(hsm_bit_val)s, .schmitt_bit = %(schmitt_bit_val)s, .lpmd_bit = %(lpmd_bit_val)s, |