diff options
author | Stephen Warren <swarren@nvidia.com> | 2015-03-25 09:58:53 -0600 |
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committer | Stephen Warren <swarren@nvidia.com> | 2015-03-25 12:02:51 -0600 |
commit | 4f47990bce794c231cfa9fb123953e496f646855 (patch) | |
tree | ca9c3d7f9d12f23c6b1ab8857533e8eb18ddd06c /soc-to-uboot-driver.py | |
parent | d5a43a4bc02221bbeb25629e9acf490e61eab552 (diff) | |
download | tegra-pinmux-scripts-4f47990bce794c231cfa9fb123953e496f646855.tar.gz |
Add support for MIPI pad ctrl groups in U-Boot driver generator
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'soc-to-uboot-driver.py')
-rwxr-xr-x | soc-to-uboot-driver.py | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/soc-to-uboot-driver.py b/soc-to-uboot-driver.py index 8469af9..50e0dc1 100755 --- a/soc-to-uboot-driver.py +++ b/soc-to-uboot-driver.py @@ -85,6 +85,28 @@ for group in soc.drive_groups_by_reg(): print('''\ PMUX_DRVGRP_COUNT, }; +''', file=f, end='') + +if len(soc.mipi_pad_ctrl_groups_by_reg()): + print('''\ + +enum pmux_mipipadctrlgrp { +''', file=f, end='') + + last_reg = soc.soc_mipipadctrl_reg_base - 4 + for group in soc.mipi_pad_ctrl_groups_by_reg(): + if group.reg != last_reg + 4: + eqs = ' = (0x%x / 4)' % (group.reg - soc.soc_mipipadctrl_reg_base) + else: + eqs = '' + print('\tPMUX_MIPIPADCTRLGRP_%s%s,' % (group.name.upper(), eqs), file=f) + + print('''\ + PMUX_MIPIPADCTRLGRP_COUNT, +}; +''', file=f, end='') + +print('''\ enum pmux_func { PMUX_FUNC_DEFAULT, @@ -107,11 +129,17 @@ print('''\ ''' % tuple(soc.soc_rsvd_base + i for i in range(4)), file=f, end='') print('#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x%x' % soc.soc_drv_reg_base, file=f) +if len(soc.mipi_pad_ctrl_groups_by_reg()): + print('#define TEGRA_PMX_SOC_MIPIPADCTRL_BASE_REG 0x%x' % soc.soc_mipipadctrl_reg_base, file=f) + if soc.soc_has_io_clamping: print('#define TEGRA_PMX_SOC_HAS_IO_CLAMPING', file=f) print('#define TEGRA_PMX_SOC_HAS_DRVGRPS', file=f) +if len(soc.mipi_pad_ctrl_groups_by_reg()): + print('#define TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS', file=f) + if soc.soc_drvgroups_have_lpmd: print('#define TEGRA_PMX_GRPS_HAVE_LPMD', file=f) @@ -193,4 +221,41 @@ print('''\ const struct pmux_pingrp_desc *tegra_soc_pingroups = %s_pingroups; ''' % soc.name, file=f, end='') +if len(soc.mipi_pad_ctrl_groups_by_reg()): + print('''\ + +#define MIPIPADCTRL_GRP(grp, f0, f1) \\ + { \\ + .funcs = { \\ + PMUX_FUNC_##f0, \\ + PMUX_FUNC_##f1, \\ + }, \\ + } + +#define MIPIPADCTRL_RESERVED {} + +static const struct pmux_mipipadctrlgrp_desc %s_mipipadctrl_groups[] = { +''' % soc.name, file=f, end='') + + headings = ('pin', 'f0', 'f1') + rows = [] + last_reg = 0 + for grp in soc.mipi_pad_ctrl_groups_by_reg(): + if grp.reg != last_reg + 4: + if last_reg: + for i in range(((grp.reg - last_reg) // 4) - 1): + rows.append('\tMIPIPACTRL_RESERVED,',) + rows.append('\t/* Offset 0x%x */' % grp.reg,) + last_reg = grp.reg + row = (grp.name.upper(),) + for i in range(2): + row += (grp.funcs[i].upper(),) + rows.append(row) + dump_c_table(headings, 'MIPIPADCTRL_GRP', rows, file=f) + + print('''\ +}; +const struct pmux_mipipadctrlgrp_desc *tegra_soc_mipipadctrl_groups = %s_mipipadctrl_groups; +''' % soc.name, file=f, end='') + f.close() |