Support Tegra210

Tegra210 changes the pinmux HW in a few ways; at least:

- The set of drive groups is much more 1:1 with the set of pins. Most
  pins have an associated drive group register as well as an associated
  pinmux register, and most drive groups cover a single pin.
- Some register fields have moved from the drive group registers into
  the pinmux registers.
- The set of available options for each pin and group varies relative to
  previous chips, and hence the register layouts vary a bit too.

This patch updates tegra-pinmux-scripts minimally to handle these
changes, to a level equivalent to the support for previous chips. For
example, some new options such as per-pin schmitt aren't handled since
the syseng-supplied pinmux spreadsheets don't provide a value for this
option.

csv-to-board-tegra124-xlsx.py is renamed to csv-to-board.py since it now
supports boards using different SoCs, and it's not worth encoding all
supported SoCs in the filename (Tegra30/114 aren't supported by it, hence
the previous naming).

Signed-off-by: Stephen Warren <swarren@nvidia.com>

1 files changed, 2 insertions, 0 deletions

diff --git a/tegra_pmx_parser_utils.py b/tegra_pmx_parser_utils.py
index cb06061..3119b6e 100644
--- a/tegra_pmx_parser_utils.py
+++ b/tegra_pmx_parser_utils.py
@@ -34,5 +34,7 @@ class TopLevelParsedObj(ReprDictObj):
             if attr in data:
                 val = data[attr]
             else:
+                if default is None:
+                    raise Exception('Missing variable ' + attr)
                 val = default
             self.__setattr__(attr, val)