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| author | Laxman Dewangan <ldewangan@nvidia.com> | 2016-05-03 00:16:44 +0530 |
|---|---|---|
| committer | Stephen Warren <swarren@nvidia.com> | 2016-05-03 10:05:17 -0600 |
| commit | 14d8f26d40d1c0c9054441ef306e6c0c18f09c78 (patch) | |
| tree | ce025375367f60bce736ecdaab103e3220251b79 /tegra_pmx_soc_parser.py | |
| parent | fe808b10578de39c397c9a4ba37a0572b6f288ee (diff) | |
| download | tegra-pinmux-scripts-14d8f26d40d1c0c9054441ef306e6c0c18f09c78.tar.gz | |
soc: Avoid parked_reg and parked_bank
NVIDIA's Tegra210 support the park bit to make pinmux configuration
enable/disable. If parked bit is 1 then configuration does not apply
and if it is 0 then pinmux configuration applies. This is to support
to avoid any glitch in pinmux configurations.
The parked bit is part of mux register and mux bank and hence it is
not required to have member for the parked_reg and parked bank very
similar to other bit field of the same register.
Remove the need of the parked register and parked bank and get whether
parked function supported or not by parked_bit.
This is to make the parked bit handling same as other fields of mux
registers.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'tegra_pmx_soc_parser.py')
| -rw-r--r-- | tegra_pmx_soc_parser.py | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/tegra_pmx_soc_parser.py b/tegra_pmx_soc_parser.py index a258f8a..891a68f 100644 --- a/tegra_pmx_soc_parser.py +++ b/tegra_pmx_soc_parser.py @@ -163,7 +163,6 @@ class Soc(TopLevelParsedObj): ('soc_mipipadctrl_reg_base', 0), ('soc_einput_b', None), ('soc_odrain_b', None), - ('soc_parked_bank', None), ('soc_parked_bit', None), ) TopLevelParsedObj.__init__(self, name, copy_attrs, data) |