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| author | Rhyland Klein <rklein@nvidia.com> | 2016-04-07 16:55:37 -0400 |
|---|---|---|
| committer | Stephen Warren <swarren@nvidia.com> | 2016-04-07 15:15:51 -0600 |
| commit | dde73ef3b7996d9687b829ada97a201db5712efa (patch) | |
| tree | 07099dce3c7183db90b309fb565164dc02451d59 /tegra_pmx_soc_parser.py | |
| parent | 8b60f5dfb9e44904ff19cde1294881d64192d5bc (diff) | |
| download | tegra-pinmux-scripts-dde73ef3b7996d9687b829ada97a201db5712efa.tar.gz | |
soc: Add support for Parked bits for Tegra210
Tegra210 has a parked bit for each pin. Add code to express this by
updating the kernel driver MACROs to add in parked_* fields so that
the kernel can handle them as it sees fit.
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'tegra_pmx_soc_parser.py')
| -rw-r--r-- | tegra_pmx_soc_parser.py | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/tegra_pmx_soc_parser.py b/tegra_pmx_soc_parser.py index 2b5d170..a258f8a 100644 --- a/tegra_pmx_soc_parser.py +++ b/tegra_pmx_soc_parser.py @@ -150,6 +150,7 @@ class Soc(TopLevelParsedObj): ('soc_drvgroups_have_lpmd', None), ('soc_drvgroups_have_schmitt', None), ('soc_pins_all_have_od', None), + ('soc_pins_all_have_parked', None), ('soc_pins_all_have_schmitt', None), ('soc_pins_have_drvtype', None), ('soc_pins_have_e_io_hv', None), @@ -162,6 +163,8 @@ class Soc(TopLevelParsedObj): ('soc_mipipadctrl_reg_base', 0), ('soc_einput_b', None), ('soc_odrain_b', None), + ('soc_parked_bank', None), + ('soc_parked_bit', None), ) TopLevelParsedObj.__init__(self, name, copy_attrs, data) |