diff options
| author | Allen Martin <amartin@nvidia.com> | 2013-09-13 10:33:49 -0700 |
|---|---|---|
| committer | Allen Martin <amartin@nvidia.com> | 2013-09-20 13:02:13 -0700 |
| commit | eb25c56e95325ca0412b50aa8650e8aa2bbe0835 (patch) | |
| tree | daf71910a97f6097b86cfa9a7bba64bcb9ef6b53 | |
| parent | 3de0b7175f5e3aaa2857b2d1ab3920a5e1824153 (diff) | |
| download | tegrarcm-eb25c56e95325ca0412b50aa8650e8aa2bbe0835.tar.gz | |
tegrarcm: Add missing SKU information
Sync up SKU numbers with TOT tegra u-boot. Also change the default
SKU print to just use the chip family name so it's more resistant to
being out of sync in the future.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
| -rw-r--r-- | src/main.c | 27 | ||||
| -rw-r--r-- | src/nv3p.h | 3 |
2 files changed, 18 insertions, 12 deletions
@@ -460,26 +460,29 @@ static void dump_platform_info(nv3p_platform_info_t *info) char *chip_name = NULL; if (info->chip_id.id == 0x20) { switch (info->sku) { - case TEGRA2_CHIP_SKU_AP20: chip_name = "ap20"; break; - case TEGRA2_CHIP_SKU_T20: chip_name = "t20"; break; + case TEGRA2_CHIP_SKU_AP20: chip_name = "ap20"; break; case TEGRA2_CHIP_SKU_T25SE: chip_name = "t25se"; break; - case TEGRA2_CHIP_SKU_AP25: chip_name = "ap25"; break; - case TEGRA2_CHIP_SKU_T25: chip_name = "t25"; break; + case TEGRA2_CHIP_SKU_AP25: chip_name = "ap25"; break; + case TEGRA2_CHIP_SKU_T25: chip_name = "t25"; break; case TEGRA2_CHIP_SKU_AP25E: chip_name = "ap25e"; break; - case TEGRA2_CHIP_SKU_T25E: chip_name = "t25e"; break; - default: chip_name = "unknown"; break; + case TEGRA2_CHIP_SKU_T25E: chip_name = "t25e"; break; + case TEGRA2_CHIP_SKU_T20: + case TEGRA2_CHIP_SKU_T20_7: + default: chip_name = "t20"; break; } } else if (info->chip_id.id == 0x30) { switch (info->sku) { - case TEGRA3_CHIP_SKU_AP30: chip_name = "ap30"; break; - case TEGRA3_CHIP_SKU_T30: chip_name = "t30"; break; - case TEGRA3_CHIP_SKU_T30S: chip_name = "t30s"; break; - default: chip_name = "unknown"; break; + case TEGRA3_CHIP_SKU_AP30: chip_name = "ap30"; break; + case TEGRA3_CHIP_SKU_T30S: chip_name = "t30s"; break; + case TEGRA3_CHIP_SKU_T33: chip_name = "t33"; break; + case TEGRA3_CHIP_SKU_T30: + default: chip_name = "t30"; break; } } else if (info->chip_id.id == 0x35) { switch (info->sku) { - case TEGRA114_CHIP_SKU_T114: chip_name = "t114"; break; - default: chip_name = "unknown"; break; + case TEGRA114_CHIP_SKU_T114: + case TEGRA114_CHIP_SKU_T114_1: + default: chip_name = "t114"; break; } } else { chip_name = "unknown"; @@ -53,6 +53,7 @@ typedef struct nv3p_state *nv3p_handle_t; // tegra2 chip sku #define TEGRA2_CHIP_SKU_AP20 0x01 +#define TEGRA2_CHIP_SKU_T20_7 0x07 #define TEGRA2_CHIP_SKU_T20 0x08 #define TEGRA2_CHIP_SKU_T25SE 0x14 #define TEGRA2_CHIP_SKU_AP25 0x17 @@ -64,9 +65,11 @@ typedef struct nv3p_state *nv3p_handle_t; #define TEGRA3_CHIP_SKU_AP30 0x87 #define TEGRA3_CHIP_SKU_T30 0x81 #define TEGRA3_CHIP_SKU_T30S 0x83 +#define TEGRA3_CHIP_SKU_T33 0X80 // tegra114 chip sku #define TEGRA114_CHIP_SKU_T114 0x00 +#define TEGRA114_CHIP_SKU_T114_1 0x01 // boot device type #define NV3P_DEV_TYPE_NAND 0x1 |