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authorTom Kelly <ctk21@cl.cam.ac.uk>2021-10-01 10:16:03 +0100
committerTom Kelly <ctk21@cl.cam.ac.uk>2021-10-01 10:16:03 +0100
commitef2eacbac36db0d78686b3ed46da13c1be2e0c7b (patch)
treef5c042915ac6f0fd117492e184b5bf6c3bb211c0 /asmcomp/mach.mli
parenta28b6d66d6618f37bfabc30d8a7e51414c326562 (diff)
parent24d7f3bde8f0af585b8328b5b4e5f386f8909cff (diff)
downloadocaml-ef2eacbac36db0d78686b3ed46da13c1be2e0c7b.tar.gz
Merge commit '24d7f3bde8f0af585b8328b5b4e5f386f8909cff' into parallel_minor_gc_4_13
Diffstat (limited to 'asmcomp/mach.mli')
-rw-r--r--asmcomp/mach.mli7
1 files changed, 7 insertions, 0 deletions
diff --git a/asmcomp/mach.mli b/asmcomp/mach.mli
index 6f34cefabf..5b5fd67aa6 100644
--- a/asmcomp/mach.mli
+++ b/asmcomp/mach.mli
@@ -108,4 +108,11 @@ val instr_cons_debug:
instruction -> instruction
val instr_iter: (instruction -> unit) -> instruction -> unit
+val operation_is_pure : operation -> bool
+ (** Returns [true] if the given operation only produces a result
+ in its destination registers, but has no side effects whatsoever:
+ it doesn't raise exceptions, it doesn't modify already-allocated
+ blocks, it doesn't adjust the stack frame, etc. *)
+
val operation_can_raise : operation -> bool
+ (** Returns [true] if the given operation can raise an exception. *)