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| author | Andy Polyakov <appro@openssl.org> | 2010-09-05 19:41:41 +0000 |
|---|---|---|
| committer | Andy Polyakov <appro@openssl.org> | 2010-09-05 19:41:41 +0000 |
| commit | 4b2603e46ca98be6036ca2ebf83f31e793047ed9 (patch) | |
| tree | b7e8d8b7fac4b51b3cc99de272b67d333cc88164 /crypto/sparccpuid.S | |
| parent | bf48836c7c0f43fd4cabde2721537f0914cfb0f4 (diff) | |
| download | openssl-new-4b2603e46ca98be6036ca2ebf83f31e793047ed9.tar.gz | |
sparcv9cap.c: disengange Solaris-specific CPU detection routine in favour
of unified procedure relying on SIGILL.
PR: 2321
Diffstat (limited to 'crypto/sparccpuid.S')
| -rw-r--r-- | crypto/sparccpuid.S | 42 |
1 files changed, 34 insertions, 8 deletions
diff --git a/crypto/sparccpuid.S b/crypto/sparccpuid.S index 1e0756a173..ae61f7f5ce 100644 --- a/crypto/sparccpuid.S +++ b/crypto/sparccpuid.S @@ -232,13 +232,23 @@ _sparcv9_rdtick: .type _sparcv9_rdtick,#function .size _sparcv9_rdtick,.-_sparcv9_rdtick +.global _sparcv9_vis1_probe +.align 8 +_sparcv9_vis1_probe: + .word 0x81b00d80 !fxor %f0,%f0,%f0 + add %sp,BIAS+2,%o1 + retl + .word 0xc19a5a40 !ldda [%o1]ASI_FP16_P,%f0 +.type _sparcv9_vis1_probe,#function +.size _sparcv9_vis1_probe,.-_sparcv9_vis1_probe + ! Probe and instrument VIS1 instruction. Output is number of cycles it ! takes to execute rdtick and pair of VIS1 instructions. US-Tx VIS unit ! is slow (documented to be 6 cycles on T2) and the core is in-order ! single-issue, it should be possible to distinguish Tx reliably... ! Observed return values are: ! -! UltraSPARC IIi 7 +! UltraSPARC IIe 7 ! UltraSPARC III 7 ! UltraSPARC T1 24 ! @@ -247,9 +257,9 @@ _sparcv9_rdtick: ! It would be possible to detect specifically US-T1 by instrumenting ! fmul8ulx16, which is emulated on T1 and as such accounts for quite ! a lot of %tick-s, couple of thousand on Linux... -.global _sparcv9_vis1_probe +.global _sparcv9_vis1_instrument .align 8 -_sparcv9_vis1_probe: +_sparcv9_vis1_instrument: .word 0x91410000 !rd %tick,%o0 .word 0x81b00d80 !fxor %f0,%f0,%f0 .word 0x85b08d82 !fxor %f2,%f2,%f2 @@ -281,12 +291,28 @@ _sparcv9_vis1_probe: .word 0x38680002 !bgu,a %xcc,.+8 mov %o3,%o0 - ! check for ASI_FP16_P is redundant... - add %sp,BIAS+2,%o1 retl - .word 0xc19a5a40 !ldda [%o1]ASI_FP16_P,%f0 -.type _sparcv9_vis1_probe,#function -.size _sparcv9_vis1_probe,.-_sparcv9_vis1_probe + nop +.type _sparcv9_vis1_instrument,#function +.size _sparcv9_vis1_instrument,.-_sparcv9_vis1_instrument + +.global _sparcv9_vis2_probe +.align 8 +_sparcv9_vis2_probe: + retl + .word 0x81b00980 !bshuffle %f0,%f0,%f0 +.type _sparcv9_vis2_probe,#function +.size _sparcv9_vis2_probe,.-_sparcv9_vis2_probe + +.global _sparcv9_fmadd_probe +.align 8 +_sparcv9_fmadd_probe: + .word 0x81b00d80 !fxor %f0,%f0,%f0 + .word 0x85b08d82 !fxor %f2,%f2,%f2 + retl + .word 0x81b80440 !fmaddd %f0,%f0,%f2,%f0 +.type _sparcv9_fmadd_probe,#function +.size _sparcv9_fmadd_probe,.-_sparcv9_fmadd_probe .global OPENSSL_cleanse .align 32 |