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| author | Justin Pettit <jpettit@nicira.com> | 2015-10-20 15:52:11 -0700 |
|---|---|---|
| committer | Justin Pettit <jpettit@ovn.org> | 2015-11-09 15:01:17 -0800 |
| commit | e0c9e58b3decbb85ebbc5a808a76ddbb4cda978a (patch) | |
| tree | 56876212be70701caaba0b5d92a9c182b690f156 /ovn/northd | |
| parent | 47f3b59b06e10b4d351d559cfd034a9147a07070 (diff) | |
| download | openvswitch-e0c9e58b3decbb85ebbc5a808a76ddbb4cda978a.tar.gz | |
ovn: Change printed stage names.
The stage names were getting long and throwing off the formatting when
dumping the logical flows.
Signed-off-by: Justin Pettit <jpettit@nicira.com>
Acked-by: Russell Bryant <rbryant@redhat.com>
Diffstat (limited to 'ovn/northd')
| -rw-r--r-- | ovn/northd/ovn-northd.c | 40 |
1 files changed, 20 insertions, 20 deletions
diff --git a/ovn/northd/ovn-northd.c b/ovn/northd/ovn-northd.c index c7d56fef1..99965841c 100644 --- a/ovn/northd/ovn-northd.c +++ b/ovn/northd/ovn-northd.c @@ -83,26 +83,26 @@ enum ovn_datapath_type { * form the stage's full name, e.g. S_SWITCH_IN_PORT_SEC, * S_ROUTER_OUT_DELIVERY. */ enum ovn_stage { -#define PIPELINE_STAGES \ - /* Logical switch ingress stages. */ \ - PIPELINE_STAGE(SWITCH, IN, PORT_SEC, 0, "switch_in_port_sec") \ - PIPELINE_STAGE(SWITCH, IN, PRE_ACL, 1, "switch_in_pre_acl") \ - PIPELINE_STAGE(SWITCH, IN, ACL, 2, "switch_in_acl") \ - PIPELINE_STAGE(SWITCH, IN, L2_LKUP, 3, "switch_in_l2_lkup") \ - \ - /* Logical switch egress stages. */ \ - PIPELINE_STAGE(SWITCH, OUT, PRE_ACL, 0, "switch_out_pre_acl") \ - PIPELINE_STAGE(SWITCH, OUT, ACL, 1, "switch_out_acl") \ - PIPELINE_STAGE(SWITCH, OUT, PORT_SEC, 2, "switch_out_port_sec") \ - \ - /* Logical router ingress stages. */ \ - PIPELINE_STAGE(ROUTER, IN, ADMISSION, 0, "router_in_admission") \ - PIPELINE_STAGE(ROUTER, IN, IP_INPUT, 1, "router_in_ip_input") \ - PIPELINE_STAGE(ROUTER, IN, IP_ROUTING, 2, "router_in_ip_routing") \ - PIPELINE_STAGE(ROUTER, IN, ARP, 3, "router_in_arp") \ - \ - /* Logical router egress stages. */ \ - PIPELINE_STAGE(ROUTER, OUT, DELIVERY, 0, "router_out_delivery") +#define PIPELINE_STAGES \ + /* Logical switch ingress stages. */ \ + PIPELINE_STAGE(SWITCH, IN, PORT_SEC, 0, "ls_in_port_sec") \ + PIPELINE_STAGE(SWITCH, IN, PRE_ACL, 1, "ls_in_pre_acl") \ + PIPELINE_STAGE(SWITCH, IN, ACL, 2, "ls_in_acl") \ + PIPELINE_STAGE(SWITCH, IN, L2_LKUP, 3, "ls_in_l2_lkup") \ + \ + /* Logical switch egress stages. */ \ + PIPELINE_STAGE(SWITCH, OUT, PRE_ACL, 0, "ls_out_pre_acl") \ + PIPELINE_STAGE(SWITCH, OUT, ACL, 1, "ls_out_acl") \ + PIPELINE_STAGE(SWITCH, OUT, PORT_SEC, 2, "ls_out_port_sec") \ + \ + /* Logical router ingress stages. */ \ + PIPELINE_STAGE(ROUTER, IN, ADMISSION, 0, "lr_in_admission") \ + PIPELINE_STAGE(ROUTER, IN, IP_INPUT, 1, "lr_in_ip_input") \ + PIPELINE_STAGE(ROUTER, IN, IP_ROUTING, 2, "lr_in_ip_routing") \ + PIPELINE_STAGE(ROUTER, IN, ARP, 3, "lr_in_arp") \ + \ + /* Logical router egress stages. */ \ + PIPELINE_STAGE(ROUTER, OUT, DELIVERY, 0, "lr_out_delivery") #define PIPELINE_STAGE(DP_TYPE, PIPELINE, STAGE, TABLE, NAME) \ S_##DP_TYPE##_##PIPELINE##_##STAGE \ |