1 files changed, 0 insertions, 84 deletions
diff --git a/target/linux/generic/backport-5.10/730-net-dsa-mt7530-setup-core-clock-even-in-TRGMII-mode.patch b/target/linux/generic/backport-5.10/730-net-dsa-mt7530-setup-core-clock-even-in-TRGMII-mode.patch
deleted file mode 100644
index f3a6f948ad..0000000000
--- a/target/linux/generic/backport-5.10/730-net-dsa-mt7530-setup-core-clock-even-in-TRGMII-mode.patch
+++ /dev/null
@@ -1,84 +0,0 @@
-From c3b8e07909dbe67b0d580416c1a5257643a73be7 Mon Sep 17 00:00:00 2001
-From: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
-Date: Fri, 12 Mar 2021 00:07:03 -0800
-Subject: [PATCH] net: dsa: mt7530: setup core clock even in TRGMII mode
-
-A recent change to MIPS ralink reset logic made it so mt7530 actually
-resets the switch on platforms such as mt7621 (where bit 2 is the reset
-line for the switch). That exposed an issue where the switch would not
-function properly in TRGMII mode after a reset.
-
-Reconfigure core clock in TRGMII mode to fix the issue.
-
-Tested on Ubiquiti ER-X (MT7621) with TRGMII mode enabled.
-
-Fixes: 3f9ef7785a9c ("MIPS: ralink: manage low reset lines")
-Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/dsa/mt7530.c | 52 +++++++++++++++++++---------------------
- 1 file changed, 25 insertions(+), 27 deletions(-)
-
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -436,34 +436,32 @@ mt7530_pad_clk_setup(struct dsa_switch *
- 			     TD_DM_DRVP(8) | TD_DM_DRVN(8));
- 
- 	/* Setup core clock for MT7530 */
--	if (!trgint) {
--		/* Disable MT7530 core clock */
--		core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
--
--		/* Disable PLL, since phy_device has not yet been created
--		 * provided for phy_[read,write]_mmd_indirect is called, we
--		 * provide our own core_write_mmd_indirect to complete this
--		 * function.
--		 */
--		core_write_mmd_indirect(priv,
--					CORE_GSWPLL_GRP1,
--					MDIO_MMD_VEND2,
--					0);
--
--		/* Set core clock into 500Mhz */
--		core_write(priv, CORE_GSWPLL_GRP2,
--			   RG_GSWPLL_POSDIV_500M(1) |
--			   RG_GSWPLL_FBKDIV_500M(25));
--
--		/* Enable PLL */
--		core_write(priv, CORE_GSWPLL_GRP1,
--			   RG_GSWPLL_EN_PRE |
--			   RG_GSWPLL_POSDIV_200M(2) |
--			   RG_GSWPLL_FBKDIV_200M(32));
--
--		/* Enable MT7530 core clock */
--		core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
--	}
-+	/* Disable MT7530 core clock */
-+	core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
-+
-+	/* Disable PLL, since phy_device has not yet been created
-+	 * provided for phy_[read,write]_mmd_indirect is called, we
-+	 * provide our own core_write_mmd_indirect to complete this
-+	 * function.
-+	 */
-+	core_write_mmd_indirect(priv,
-+				CORE_GSWPLL_GRP1,
-+				MDIO_MMD_VEND2,
-+				0);
-+
-+	/* Set core clock into 500Mhz */
-+	core_write(priv, CORE_GSWPLL_GRP2,
-+		   RG_GSWPLL_POSDIV_500M(1) |
-+		   RG_GSWPLL_FBKDIV_500M(25));
-+
-+	/* Enable PLL */
-+	core_write(priv, CORE_GSWPLL_GRP1,
-+		   RG_GSWPLL_EN_PRE |
-+		   RG_GSWPLL_POSDIV_200M(2) |
-+		   RG_GSWPLL_FBKDIV_200M(32));
-+
-+	/* Enable MT7530 core clock */
-+	core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
- 
- 	/* Setup the MT7530 TRGMII Tx Clock */
- 	core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);