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From 9fe99de01440d9ede74d447ac76e9c445d8daae9 Mon Sep 17 00:00:00 2001
From: Yang Yingliang <yangyingliang@huawei.com>
Date: Sat, 29 May 2021 11:04:39 +0800
Subject: [PATCH] net: dsa: qca8k: add missing check return value in
qca8k_phylink_mac_config()
Now we can check qca8k_read() return value correctly, so if
it fails, we need return directly.
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
---
drivers/net/dsa/qca8k.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
--- a/drivers/net/dsa/qca8k.c
+++ b/drivers/net/dsa/qca8k.c
@@ -1128,6 +1128,7 @@ qca8k_phylink_mac_config(struct dsa_swit
{
struct qca8k_priv *priv = ds->priv;
u32 reg, val;
+ int ret;
switch (port) {
case 0: /* 1st CPU port */
@@ -1198,7 +1199,9 @@ qca8k_phylink_mac_config(struct dsa_swit
qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN);
/* Enable/disable SerDes auto-negotiation as necessary */
- qca8k_read(priv, QCA8K_REG_PWS, &val);
+ ret = qca8k_read(priv, QCA8K_REG_PWS, &val);
+ if (ret)
+ return;
if (phylink_autoneg_inband(mode))
val &= ~QCA8K_PWS_SERDES_AEN_DIS;
else
@@ -1206,7 +1209,9 @@ qca8k_phylink_mac_config(struct dsa_swit
qca8k_write(priv, QCA8K_REG_PWS, val);
/* Configure the SGMII parameters */
- qca8k_read(priv, QCA8K_REG_SGMII_CTRL, &val);
+ ret = qca8k_read(priv, QCA8K_REG_SGMII_CTRL, &val);
+ if (ret)
+ return;
val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX |
QCA8K_SGMII_EN_TX | QCA8K_SGMII_EN_SD;
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