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| author | Ray Essick <essick@google.com> | 2017-08-24 05:32:42 -0700 |
|---|---|---|
| committer | Felicia Lim <flim@google.com> | 2017-08-24 05:32:42 -0700 |
| commit | 492fc927268752da4cae855652b34cbaa93ebe44 (patch) | |
| tree | e613c40c2b4810728a801ee4cc353f9233a1f884 /celt | |
| parent | ca3cb3234181980ac9ccf2b49bc6a10255c219f4 (diff) | |
| download | opus-492fc927268752da4cae855652b34cbaa93ebe44.tar.gz | |
fix alignment exceptions
some SSE optimizations were using an instruction sequence that required
128-bit alignment, even though this is not always guaranteed. The error
was in handling a 64-bit entity; made the same macro changes that had
been done previously for 32-bit entities.
Signed-off-by: Felicia Lim <flim@google.com>
Diffstat (limited to 'celt')
| -rw-r--r-- | celt/x86/x86cpu.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/celt/x86/x86cpu.h b/celt/x86/x86cpu.h index 04fd48aa..1e2bf17b 100644 --- a/celt/x86/x86cpu.h +++ b/celt/x86/x86cpu.h @@ -82,7 +82,9 @@ int opus_select_arch(void); (_mm_cvtepi8_epi32(*(__m128i *)(x))) #endif -# if !defined(__OPTIMIZE__) +/* similar reasoning about the instruction sequence as in the 32-bit macro above, + */ +# if defined(__clang__) || !defined(__OPTIMIZE__) # define OP_CVTEPI16_EPI32_M64(x) \ (_mm_cvtepi16_epi32(_mm_loadl_epi64((__m128i *)(x)))) # else |