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path: root/celt/laplace.c
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* Merge commit '390c89225d'Jean-Marc Valin2012-04-241-2/+2
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| * s/FOUNDATION/COPYRIGHT OWNER/ in CELT code and "glue code"Jean-Marc Valin2012-04-201-2/+2
| | | | | | | | Also added 3rd clause to "master" COPYING file
* | Cast a factor to maintain precision on 16 bit systems.Ralph Giles2012-04-021-1/+2
|/ | | | | | | | | | | | | | | | | The multiply would overflow with 16 bit ints. Thanks to Riccardo Micci for pointing out the issue. Thanks to Tim Terriberry for the valid range of the decay argument. Note that ft is unsigned, but always less than 32736, so we could use a 16 bit signed type here if it allows the compiler to produce faster code (with signed 16*16 and 16*32 multiplies). In the absense of actual cycle counts from a real platform, I've left it as an unsigned for the sake of readability. For similar reasons we cast (16384-decay) to a signed integer even though it is also always positive.
* renames the libcelt/ directory to celt/Jean-Marc Valin2011-09-131-0/+133
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* Moved all SILK source code to the silk/ directoryJean-Marc Valin2011-04-281-6/+0
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* Loss rate adaptation for the CELT layerJean-Marc Valin2011-04-251-5/+5
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* draft updateJean-Marc Valin2011-03-311-5/+5
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* Build fixesJean-Marc Valin2011-03-231-5/+5
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* Making mode switching use the same window as CELT (squared)Jean-Marc Valin2011-03-211-5/+5
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* CELT updateJean-Marc Valin2011-03-181-5/+5
| | | | With minor fixes
* More project files updateJean-Marc Valin2011-03-181-5/+5
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* Fixes a few PLC/DTX bugs due to the recent decode API changeJean-Marc Valin2011-03-161-5/+5
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* Adding constrained VBR modeJean-Marc Valin2011-03-141-5/+5
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* Draft update (allocationGregory Maxwell2011-03-141-5/+5
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* Disable newly introduced CELT signallingJean-Marc Valin2011-03-111-5/+5
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* Nothing to see hereJean-Marc Valin2011-03-101-5/+5
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* CELT updateJean-Marc Valin2011-03-091-18/+5
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* Support for glitchles mode switchingJean-Marc Valin2011-03-071-5/+18
| | | | | | Uses a 5ms redundant CELT frame embedded into the SILK or hybrid packet to handle the switching. It's still possible to use the PLC-based method when no redundant packet is included.
* SILK/CELT updateJean-Marc Valin2011-02-281-5/+5
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* preparing the next versionJean-Marc Valin2011-02-141-5/+5
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* missing filesJean-Marc Valin2011-02-141-10/+5
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* SILK and CELT updatesJean-Marc Valin2011-02-141-5/+10
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* Update for in-band FECKoen Vos2011-02-141-5/+5
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* draft dateJean-Marc Valin2011-02-041-0/+6
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* CELT updateJean-Marc Valin2011-02-041-6/+0
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* Tuning the hybrid bit-rate splitKoen Vos2011-02-041-24/+5
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* Oops, fixed the CELT versionJean-Marc Valin2011-02-031-0/+25
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* Update Opus range coder due to CELT refactoring.Timothy B. Terriberry2011-02-031-6/+0
| | | | | The byte buffer is now part of the range coder struct itself, and rangeenc.c and rangedec.c have gone away.
* CELT update, version numbersJean-Marc Valin2011-02-031-5/+5
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* Build fixesJean-Marc Valin2011-02-031-5/+5
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* Oops, had inverted some tuning linesJean-Marc Valin2011-02-031-5/+5
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* Hybrid mode tuningKarsten Vandborg Sorensen2011-02-031-7/+5
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* CELT updateJean-Marc Valin2011-02-031-5/+7
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* Some work on the buildJean-Marc Valin2011-02-031-5/+5
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* Enabling the CELT post-filter in OpusJean-Marc Valin2011-02-021-5/+5
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* CELT updateJean-Marc Valin2011-02-021-5/+5
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* Enabling real CELT VBRJean-Marc Valin2011-02-011-5/+5
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* CELT updateJean-Marc Valin2011-02-011-5/+5
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* CELT updateJean-Marc Valin2011-01-311-5/+5
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* Fixes resampling in CELT-only modeJean-Marc Valin2011-01-311-5/+5
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* Merge stereo switching CELT APIJean-Marc Valin2011-01-311-5/+5
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* Updated to CELT's new APIJean-Marc Valin2011-01-301-5/+5
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* CELT updateJean-Marc Valin2011-01-221-5/+5
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* CELT updateJean-Marc Valin2011-01-181-5/+5
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* CELT updated to 0.9.0 (+ PLC fix)Jean-Marc Valin2010-11-081-5/+5
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* Renamed to OpusJean-Marc Valin2010-10-151-5/+5
| | | | And updated CELT
* Renamed to HarmonyJean-Marc Valin2010-10-091-5/+5
| | | | Also a CELT update
* CELT updateJean-Marc Valin2010-09-211-7/+5
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* CELT updateJean-Marc Valin2010-09-071-5/+7
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* CELT updateJean-Marc Valin2010-08-311-5/+5
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