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| author | Sean V Kelley <sean.v.kelley@linux.intel.com> | 2020-05-11 10:46:18 -0700 |
|---|---|---|
| committer | Martin Mares <mj@ucw.cz> | 2020-05-25 12:30:28 +0200 |
| commit | 5667015e20c0402cfa059a226706b0f7d35945d2 (patch) | |
| tree | f0a84116fb152ffc77ec8f381a8e8df8b84003b7 /lib/header.h | |
| parent | 2500d179f758ded541363d028ecd536865fd325e (diff) | |
| download | pciutils-test.tar.gz | |
pciutils: Decode Compute eXpress Link DVSECtest
Compute eXpress Link[1] is a new CPU interconnect created with
workload accelerators in mind. The interconnect relies on PCIe
electrical and physical interconnect for communication via a Flex Bus
port which allows designs to choose between providing PCIe or CXL.
This patch introduces basic support for lspci decode of CXL and
builds upon the existing Designated Vendor-Specific support in
lspci through identification of a supporting CXL device using DVSEC
Vendor ID and DVSEC ID.
[1] https://www.computeexpresslink.org/
Signed-off-by: Sean V Kelley <sean.v.kelley@linux.intel.com>
Diffstat (limited to 'lib/header.h')
| -rw-r--r-- | lib/header.h | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/lib/header.h b/lib/header.h index 76ac8f2..56b2c39 100644 --- a/lib/header.h +++ b/lib/header.h @@ -1055,6 +1055,27 @@ /* PCIe Designated Vendor-Specific Capability */ #define PCI_DVSEC_HEADER1 4 /* Designated Vendor-Specific Header 1 */ #define PCI_DVSEC_HEADER2 8 /* Designated Vendor-Specific Header 2 */ +#define PCI_DVSEC_INTEL_CXL 0 /* Designated Vendor-Specific ID for Intel CXL */ +#define PCI_DVSEC_VENDOR_ID_CXL 0x1e98 /* Designated Vendor-Specific Vendor ID for CXL */ + +/* PCIe CXL Designated Vendor-Specific Capabilities, Control, Status */ +#define PCI_CXL_CAP 0x0a /* CXL Capability Register */ +#define PCI_CXL_CAP_CACHE 0x0001 /* CXL.cache Protocol Support */ +#define PCI_CXL_CAP_IO 0x0002 /* CXL.io Protocol Support */ +#define PCI_CXL_CAP_MEM 0x0004 /* CXL.mem Protocol Support */ +#define PCI_CXL_CAP_MEM_HWINIT 0x0008 /* CXL.mem Initalizes with HW/FW Support */ +#define PCI_CXL_CAP_HDM_CNT(x) (((x) & (3 << 4)) >> 4) /* CXL Number of HDM ranges */ +#define PCI_CXL_CAP_VIRAL 0x4000 /* CXL Viral Handling Support */ +#define PCI_CXL_CTRL 0x0c /* CXL Control Register */ +#define PCI_CXL_CTRL_CACHE 0x0001 /* CXL.cache Protocol Enable */ +#define PCI_CXL_CTRL_IO 0x0002 /* CXL.io Protocol Enable */ +#define PCI_CXL_CTRL_MEM 0x0004 /* CXL.mem Protocol Enable */ +#define PCI_CXL_CTRL_CACHE_SF_COV(x) (((x) & (0x1f << 3)) >> 3) /* Snoop Filter Coverage */ +#define PCI_CXL_CTRL_CACHE_SF_GRAN(x) (((x) & (0x7 << 8)) >> 8) /* Snoop Filter Granularity */ +#define PCI_CXL_CTRL_CACHE_CLN 0x0800 /* CXL.cache Performance Hint on Clean Evictions */ +#define PCI_CXL_CTRL_VIRAL 0x4000 /* CXL Viral Handling Enable */ +#define PCI_CXL_STATUS 0x0e /* CXL Status Register */ +#define PCI_CXL_STATUS_VIRAL 0x4000 /* CXL Viral Handling Status */ /* Access Control Services */ #define PCI_ACS_CAP 0x04 /* ACS Capability Register */ |