libpci: Add Intel Type 1 implementation for memory mapped systems

Lot of non-x86 platforms also support Intel Type 1 mechanism. x86 IO ports
CF8 and CFC are on these platforms mapped into standard memory space.
Address mapping itself is platform or board specific and there is no
default value.

Lot of ARM boards with multiple PCIe controllers are multi-domain and each
PCI domain has its own CF8/CFC (address/data) registers mapped into memory
space.

Add new mmio-conf1 backend which access CF8/CFC ports via MMIO and define
new config option mmio-conf1.addrs which specify list of address/data
register pairs in memory space for each PCI domain. Format of this option
is: 0xaddr1/0xdata1,0xaddr2/0xdata2,...

1 files changed, 1 insertions, 0 deletions

diff --git a/lib/pci.h b/lib/pci.h
index 14c1301..f6197c4 100644
--- a/lib/pci.h
+++ b/lib/pci.h
@@ -45,6 +45,7 @@ enum pci_access_type {
   PCI_ACCESS_HURD,			/* GNU/Hurd */
   PCI_ACCESS_WIN32_CFGMGR32,		/* Win32 cfgmgr32.dll */
   PCI_ACCESS_WIN32_SYSDBG,		/* Win32 NT SysDbg */
+  PCI_ACCESS_MMIO_TYPE1,		/* MMIO ports, type 1 */
   PCI_ACCESS_MAX
 };