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* Released as v3.10.0.v3.10.0Martin Mares2023-05-011-1/+1
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* Documented that pci_(read|write)_block are little-endianMartin Mares2023-03-051-3/+6
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* Parameters: Keep the list sorted and remove duplicatesMartin Mares2023-03-051-4/+18
| | | | | | When multiple back-ends use the same option (e.g., "devmem.path"), they tend to define it each. This is not nice, but before we generalize these options properly, let us at least remove the duplicate definitions.
* libpci: Add PCIe ECAM access methodPali Rohár2023-03-056-5/+1119
| | | | | | | | | | This is a new direct hardware access method via PCIe ECAM (Enhanced Configuration Access Mechanism). It is available on all PCIe-compliant hardware. Requires root privileges and access to physical memory. ECAM mapping can be specified manually via a new ecam.addrs parameter or can be read from ACPI MCFG table. ACPI MCFG table can be located in the system or read from x86 BIOS memory.
* Fix bug in previous commitMartin Mares2023-03-041-1/+1
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* win32-cfgmgr32: Clean up initializationMartin Mares2023-03-043-36/+38
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* Merge remote-tracking branch 'pali/win32-cfgmgr32'Martin Mares2023-03-043-15/+125
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| * libpci: win32-cfgmgr32: Add support for accessing config space via other backendPali Rohár2023-01-043-15/+125
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Extend win32-cfgmgr32 backend and add a new option win32.cfgmethod for specifying other backend for accessing PCI config space. There are more config space access methods available on Windows and each is working only sometimes (either requires special privileges or special setup). So by default try to choose the first working one via order defined in pci probe_sequence[] array. If none is available then emulate PCI config space like before this change. Function pci_init_v35() is extended and renamed to pci_init_internal() to optionally do not throw errors and allow to specify one access method which will be skipped in AUTO mode. This is used to prevent choosing win32-cfgmgr32 as config space access method for win32-cfgmgr32.
* | Merge remote-tracking branch 'pali/windows'Martin Mares2023-03-042-6/+157
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| * | libpci: windows: Define ERROR_NOT_FOUNDPali Rohár2022-11-211-0/+4
| | | | | | | | | | | | Fix compile issues with older toolchain which does not define ERROR_NOT_FOUND macro.
| * | libpci: windows: Handle long paths generated by GetModuleFileName()Pali Rohár2022-11-181-1/+8
| | | | | | | | | | | | | | | | | | | | | C function fopen() implemented by msvcrt.dll requires special prefix "\\\\?\\" for paths longer than 260 bytes. Because GetModuleFileName() returns absolute path, it may be longer than 260 bytes. Add fixup to handle long paths.
| * | libpci: windows: Fix path returned by GetModuleFileName()Pali Rohár2022-11-181-3/+36
| | | | | | | | | | | | | | | GetModuleFileName() on Windows 10 has bugs and returns bogus path. Implement fixups to make path usable for later fopen() call.
| * | libpci: djgpp: Allow to specify empty IDSDIR=Pali Rohár2022-11-181-3/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | Like for windows builds this will cause to load pci.ids file from the same directory where is stored application binary. Code is same as for Windows, just djgpp uses global symbol __dos_argv0 instead of _pgmptr. Tested with following compile command: make CROSS_COMPILE=i586-pc-msdosdjgpp- HOST=i586-djgpp ZLIB=no DNS=no IDSDIR=
| * | libpci: windows: Fix locating path to pci.ids file for DLL buildsPali Rohár2022-11-181-1/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When using shared libpci DLL library, it is expected that pci.ids file is stored in directory where is also libpci DLL library and not in directory where is application executable. Based on the build mode and compile options, choose the appropriate function for retrieving path to the libpci DLL library or application executable. Also pass correct module argument to GetModuleFileName() call.
| * | libpci: windows: Fix usage of GetModuleFileName()Pali Rohár2022-11-181-5/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Module file name can have arbitrary length despite all MS examples say about MAX_PATH upper limit. This limit does not apply for example when executable is running from network disk with very long UNC paths or when using "\\??\\" prefix for specifying executable binary path. So handle buffer truncatenation by retrying GetModuleFileName() call with larger buffer. Fixes loading of pci.ids file when lspci.exe binary is running from network drive with path longer than 260 bytes.
* | | Merge remote-tracking branch 'pali/mmio-ports'Martin Mares2023-03-041-4/+4
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| * | | libpci: mmio-ports: Fix support for 64-bit non-LLP64 systemsPali Rohár2023-01-291-4/+4
| | |/ | |/| | | | | | | | | | | | | On 64-bit non-LLP64 systems is type long 64-bit. On 32-bit and 64-bit LLP64 systems is type long only 32-bit. But readl() and writel() functions works with 32-bit PCI word. Fix it for non-LLP64 systems by using type u32.
* | | Filters: Allow leading "0x" for backward compatibilityMartin Mares2023-03-041-0/+5
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* | | Fix versioned symbol aliases when used with link-time optimizationMartin Mares2022-12-281-2/+2
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* | Released as 3.9.0v3.9.0Martin Mares2022-11-201-1/+1
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* libpci: mmio-ports: Add Extended PCIe Intel Type 1 access methodPali Rohár2022-11-184-17/+87
| | | | | | | Extended method allows to access all PCIe registers, including extended registers starting at 0x100 offset. This method uses 4 reserved buts above bus bits for PCIe registers. On ARM platforms it is very common for PCIe controllers. Like standard method, it needs to be properly configured.
* Merge remote-tracking branch 'pali/intel-conf1-memio'Martin Mares2022-11-182-6/+19
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| * libpci: mmio-ports: Check for write access to /dev/mem in detect methodPali Rohár2022-11-181-2/+2
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| * libpci: mmio-ports: Add configure note messagesPali Rohár2022-11-181-3/+3
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| * libpci: mmio-ports: Bypass CPU cache and add barriers for read/writePali Rohár2022-11-181-1/+14
| | | | | | | | | | Between accessing address address and data I/O ports it is needed to issue barriers. Use explicit readl() for barrier and O_DSYNC to bypass CPU cache.
* | libpci: Add new windows kldbgdrv.sys implementationPali Rohár2022-11-187-2/+813
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Microsoft Kernel Local Debugging Driver (kldbgdrv.sys) allow access for userspace processes to the PCI config space. It supports access up to 65536 domains and whole 4096 bytes long extended PCIe config space. Driver is signed by Microsoft and is available for both 32-bit and 64-bit systems. Driver is not part of Windows system and has to be installed via WinDbg installation package. Standalone installers for WinDbg 6.12.2.633 version: https://download.microsoft.com/download/A/6/A/A6AC035D-DA3F-4F0C-ADA4-37C8E5D34E3D/setup/WinSDKDebuggingTools_amd64/dbg_amd64.msi https://download.microsoft.com/download/A/6/A/A6AC035D-DA3F-4F0C-ADA4-37C8E5D34E3D/setup/WinSDKDebuggingTools/dbg_x86.msi This kldbgdrv.sys API is used by the !pci command of new WinDbg kernel debugger for displaying PCI config space. API of this driver is available only for processes with Debug privilege and only if system was booted with Debugging option.
* | Disable mmio-ports on platforms where it does not make much senseMartin Mares2022-11-181-8/+0
| | | | | | | | Feel free to re-enable it if you find it useful.
* | Merge remote-tracking branch 'pali/intel-conf1-memio'Martin Mares2022-11-189-8/+434
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| * libpci: Add Intel Type 1 implementation for memory mapped systemsPali Rohár2022-11-056-1/+417
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Lot of non-x86 platforms also support Intel Type 1 mechanism. x86 IO ports CF8 and CFC are on these platforms mapped into standard memory space. Address mapping itself is platform or board specific and there is no default value. Lot of ARM boards with multiple PCIe controllers are multi-domain and each PCI domain has its own CF8/CFC (address/data) registers mapped into memory space. Add new mmio-conf1 backend which access CF8/CFC ports via MMIO and define new config option mmio-conf1.addrs which specify list of address/data register pairs in memory space for each PCI domain. Format of this option is: 0xaddr1/0xdata1,0xaddr2/0xdata2,...
| * libpci: Add auxiliary data member to struct pci_access for use by the back-endPali Rohár2022-11-051-0/+1
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| * libpci: Add new internal function pci_generic_scan_domain()Pali Rohár2022-11-054-7/+16
| | | | | | | | | | Function pci_generic_scan() scans PCI domain 0. This new function pci_generic_scan_domain() scans specified PCI domain number.
* | Merge remote-tracking branch 'jphaws/cxl-dvsec-decoded'Martin Mares2022-11-181-0/+80
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| * | lspci: Add support for Non-CXL Function Map DVSECJaxon Haws2022-11-161-0/+11
| | | | | | | | | | | | | | | | | | | | | Add Non-CXL Function Map DVSEC Registers 0-7 decoding according to DVSEC Revision ID 0. Signed-off-by: Jaxon Haws <jaxon.haws@amd.com>
| * | lspci: Add support for CXL MLD DVSECJaxon Haws2022-11-161-0/+5
| | | | | | | | | | | | | | | | | | | | | Add MLD DVSEC decoding for CXL device accoring to DVSEC revision ID 0. Decode Number of Logical Devices Supported. Signed-off-by: Jaxon Haws <jaxon.haws@amd.com>
| * | lspci: Add support for CXL GPF Port DVSECJaxon Haws2022-11-161-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | Add Global Persistent Flush DVSEC decoding for CXL port according to DVSEC Revision ID 0. Decode GPF Phase 1 Control and GPF Phase 2 Control. Signed-off-by: Jaxon Haws <jaxon.haws@amd.com>
| * | lspci: Add support for CXL Flex Bus DVSECJaxon Haws2022-11-161-0/+40
| | | | | | | | | | | | | | | | | | | | | Add DVSEC Flex Bus Port for CXL devices according to DVSEC Revision ID 1, capability decoding, control decoding, and status decoding. Signed-off-by: Jaxon Haws <jaxon.haws@amd.com>
| * | lspci: Add support for CXL GPF Device DVSECJaxon Haws2022-11-021-0/+13
| |/ | | | | | | | | | | | | | | Add Global Persistent Flush DVSEC decoding for CXL device according to DVSEC Revision ID 0. Decode GPF Phase 2 Duration and GPF Phase 2 Power. Signed-off-by: Jaxon Haws <jaxon.haws@amd.com>
* | Merge remote-tracking branch 'pali/i386-io-windows'Martin Mares2022-11-131-1/+2
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| * | libpci: i386-io-windows.h: Improve ProcessUserModeIOPL error messagePali Rohár2022-10-301-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | Show error message from intel_setup_io() function into debug area instead of error area. This is what other backends do as intel_setup_io() is called during quite detect phase, which may fail. Also show human readable failure instead of magic code number.
* | | Merge remote-tracking branch 'pali/linux-ioperm'Martin Mares2022-11-131-2/+46
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| * | | i386-io-linux: Prefer usage of ioperm()Pali Rohár2022-11-061-2/+46
| | |/ | |/| | | | | | | | | | | | | | | | Since Linux 2.6.8, it is possible to use ioperm() syscall to gain access for all I/O ports. Because iopl() syscall before Linux 5.5 allowed userspace to disable interrupts, prefer usage of ioperm() syscall and ask for access only for PCI ports.
* | | Merge remote-tracking branch 'pali/win32-cfgmgr32'Martin Mares2022-11-131-4/+14
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| * | | libpci: win32-cfgmgr32: Fix typoPali Rohár2022-11-061-1/+1
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| * | | libpci: win32-cfgmgr32: Fix parsing paths in NT formatPali Rohár2022-11-061-3/+13
| |/ / | | | | | | | | | NT namespace separator may be single or double backslash.
* | | Merge remote-tracking branch 'pali/i386-ports'Martin Mares2022-11-131-8/+12
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| * | | i386-ports: Fix intel_io_lock usagePali Rohár2022-11-061-8/+12
| |/ / | | | | | | | | | | | | | | | Do not call pci_generic_block_read() and pci_generic_block_write() functions when io is locked. These functions call back same backend read/write function which tries to lock and unlock io again.
* | | windows: Codepage in resource file is 16-bit numberPali Rohár2022-11-091-1/+1
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* | | windows: Put name and version information into lspci/setpci executablesPali Rohár2022-11-052-5/+11
|/ / | | | | | | | | Extend existing .in resource template file and generate resource objects also for lspci.exe and setpci.exe executables.
* | cxl: Fix Register Locator DVSEC decodingJaxon Haws2022-10-311-6/+1
|/ | | | | | | | Fix decoding of register blocks by introducing offset to position calculation (8.1.9 of CXL 3.0 spec) and removed unused defines for Register Locator DVSEC. Signed-off-by: Jaxon Haws <jaxon.haws@amd.com>
* Merge remote-tracking branch 'pali/win32-dll'Martin Mares2022-10-307-9/+147
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