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* lspci: Fix detection of memory space barPali Rohár2022-04-161-1/+1
* Fix lspci: Power Management Control/Status PCI to PCI Bridge Support ExtensionsMikhail Bratchikov2022-04-151-2/+2
* lspci: Decode PCIe 6.0 Slot Power Limit valuesPali Rohár2022-02-261-9/+7
* lspci: Replace unsigned long long type by u64 and %llx format by PCI_U64_FMT_XPali Rohár2022-02-101-1/+1
* lspci: Improvements to PCIe link speed downgrade reportingMartin Mares2022-01-211-8/+11
* Add PCIe 3.0+ decoding of the LnkCtl2 Compliance Preset/De-emphasis fieldLennert Buytenhek2021-12-281-2/+31
* lspci: Show Slot Power Limit values above EFhPali Rohár2021-12-271-8/+22
* lspci: Add PCIe 6.0 data rate (64 GT/s) supportGustavo Pimentel2020-12-061-0/+4
* lspci: Decode 10-Bit Tag Requester EnableDongdong Liu2020-09-021-1/+2
* lspci: Adjust PCI_EXP_DEV2_* to PCI_EXP_DEVCTL2_* macro definitionDongdong Liu2020-09-021-10/+10
* lspci: Use commas more consistentlyBjorn Helgaas2020-05-251-12/+12
* lspci: Decode PCIe Link Capabilities 2, expand Link Status 2Bjorn Helgaas2020-05-251-2/+91
* lspci: Reorder Express Root Complex registers to Cap, Ctl, StaBjorn Helgaas2020-01-211-5/+7
* lspci: Add PCIe 5.0 data rate (32 GT/s) supportGustavo Pimentel2019-06-041-0/+4
* lspci: Decode all defined fields in the Device Capabilities 2 registerFrederick Lawler2019-02-221-6/+77
* "Function-Level Reset" device capability is displayed for RCiEPMartin Mares2018-12-311-2/+2
* Print Root complex related registers on RCEC, tooMasanobu SAITOH2018-10-141-2/+2
* lspci: Decode Null CapabilityBjorn Helgaas2018-04-201-0/+3
* lspci: Clarify unknown capability IDsBjorn Helgaas2018-04-201-1/+1
* lspci: Avoid "%1$c" style format strings in HT capabilityMartin Mares2018-03-241-48/+62
* lspci: Report if the PCIe link speed/width is full or downgradedMartin Mares2018-03-161-6/+22
* lspci: Make DevCtl, DevSta, and AER decoding more consistentBjorn Helgaas2018-03-021-2/+2
* lspci: Fix wrong read size for RootStaJeffy Chen2017-07-051-1/+1
* lspci: Use #defines for greppabilityBjorn Helgaas2017-04-291-10/+10
* lspci: Decode only supported ASPM exit latenciesBjorn Helgaas2017-04-291-5/+14
* lspci: Decode "Slot Implemented" for PCI/PCI-X to PCIe BridgesBjorn Helgaas2017-04-291-1/+3
* lspci: Indent PCIe Capability DevCap2 & DevCtl2 correctlyBjorn Helgaas2017-04-291-2/+2
* lspci: Decode AER Root Error Command, Root Error Status, Error SourceBjorn Helgaas2017-04-291-7/+9
* ls-caps: Minor cleanup of cap_express_dev2()Martin Mares2017-02-151-2/+1
* pciutils: Add decode for Atomic Ops in lspciSatanand Burla2017-02-151-0/+47
* lspci: Support GEN4 speed (16GT/s)Gavin Shan2017-02-151-0/+4
* Add lspci support for Enhanced Allocation Capability.David Daney2016-01-031-0/+156
* lspci: Decode DevCap SlotPowerLimit for all components with Upstream PortsBjorn Helgaas2015-12-221-1/+2
* Add virtio vendor capability supportGerd Hoffmann2015-01-221-1/+1
* Avoid C99 constructionsFrançois Revol2014-11-011-1/+1
* lspci: Decode ASPMOptComp bit in LnkCap registerMartin Mares2014-02-251-2/+3
* lspci: Drop PCIe LnkCtl "Retrain Link" decodingBjorn Helgaas2013-11-101-2/+1
* lspci: Decode PCIe LnkCtl "Read Completion Boundary" for PCIe-to-PCI bridgesBjorn Helgaas2013-11-101-1/+1
* lspci: Clarify "PCIe-to-PCI/PCI-X" desc and Bridge Retry Config EnableBjorn Helgaas2013-11-101-2/+2
* lspci: Decode PCIe DevCap/DevCtl FLReset only for EndpointsBjorn Helgaas2013-11-101-4/+7
* lspci: Decode PCIe DevCap "Acceptable Latencies" only for EndpointsBjorn Helgaas2013-11-101-2/+5
* lspci: Label PCIe LnkCap "L0s Exit Latency" as "L0s", not "L0"Bjorn Helgaas2013-11-101-1/+1
* lspci: Decode PCIe Link registers only for devices with linksBjorn Helgaas2013-11-101-2/+7
* lspci: Fully decode ASPM support from Link CapabilitiesBjorn Helgaas2013-05-201-0/+2
* lspci: Display CardBus bridge capabilitiesMatthew Wilcox2013-04-201-2/+2
* Display whether LTR/OBFF are supported and enabledMika Westerberg2012-06-121-4/+40
* Only decode defined fields of PCI Express Link Control 2Ben Hutchings2012-05-281-7/+13
* Add PCIe Gen 3 speeds and link status fieldsMartin Mares2011-11-081-2/+14
* Improved formatting of PCIe port/slot capabilitiesMartin Mares2010-01-281-2/+2
* Updated (c) years.Martin Mares2010-01-241-1/+1
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