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* Add test case with multidomain Freescale P2020 PCIe hierarchyPali Rohár2023-04-291-0/+1548
* lspci: Add test case for CXL deviceJaxon Haws2022-11-161-0/+258
* pciutils: Add decode support for Data Object Exchange Extended CapabilityJonathan Cameron2022-02-261-0/+302
* lspci: Update tests files with VF 10-Bit Tag RequesterDongdong Liu2022-01-213-6/+6
* pciutils: Add decode support for RCECsSean V Kelley2020-09-021-0/+299
* CXL: Capability vendor ID changedSean V Kelley2020-05-271-95/+108
* lspci: Decode the (virtual) resizeble BAR capabilityMartin Mares2020-05-251-0/+258
* Tests: cap-dvsec was superseded by cap-dvsec-cxlMartin Mares2020-05-251-340/+0
* Tests: cap-dvsec-cxl had tabs erroneously expanded to spacesMartin Mares2020-05-251-83/+83
* pciutils: Decode Compute eXpress Link DVSECSean V Kelley2020-05-251-0/+340
* pciutils: Decode available DVSEC detailsSean V Kelley2020-05-251-0/+340
* lspci: Decode PCIe Link Capabilities 2, expand Link Status 2Bjorn Helgaas2020-05-251-0/+1317
* lspci: Decode all defined fields in the Device Capabilities 2 registerFrederick Lawler2019-02-221-11/+17
* lspci: Decode Multicast Extended CapabilityBjorn Helgaas2018-11-121-0/+257
* Added test cases for topology computationMartin Mares2018-08-122-0/+7350
* lspci: Avoid "%1$c" style format strings in HT capabilityMartin Mares2018-03-241-0/+99
* lspci: Decode "VGA 16-bit decode" in bridge control registerBjorn Helgaas2017-12-311-0/+129
* lspci: Decode only supported ASPM exit latenciesBjorn Helgaas2017-04-291-0/+327
* lspci: Decode "Slot Implemented" for PCI/PCI-X to PCIe BridgesBjorn Helgaas2017-04-291-0/+288
* lspci: Indent PCIe Capability DevCap2 & DevCtl2 correctlyBjorn Helgaas2017-04-291-0/+327
* lspci: Include "ECRC" in the ECRC generate/check labelsBjorn Helgaas2017-04-291-0/+327
* lspci: Decode AER Root Error Command, Root Error Status, Error SourceBjorn Helgaas2017-04-291-0/+626
* lspci: Dump AER Header LogBjorn Helgaas2017-04-291-0/+323
* lspci: Decode AER Multiple Header and TLP Prefix Log bitsBjorn Helgaas2017-04-291-0/+322
* pciutils: Add test case for pci atomic opsSatanand Burla2017-02-151-0/+54
* pciutils: Update the tests/cap-l1-pm with actual device dataRajat Jain2016-10-031-24/+303
* lspci: Add test case for PTMYong, Jonathan2016-05-192-0/+576
* Add support for Downstream Port ContainmentKeith Busch2016-05-141-0/+91
* Add lspci support for Enhanced Allocation Capability.David Daney2016-01-031-0/+324
* Decode PASID and PRI extended capabilitiesDavid Woodhouse2015-10-271-0/+293
* Added test case for virtioMartin Mares2015-01-221-0/+41
* Added a test case for the L1 PM capabilityMartin Mares2013-06-111-0/+26
* Added a test case for the VC capability with a port arbitration tableMartin Mares2010-01-311-0/+257
* Added a test case for Virtual Channel and Root Complex Link capsMartin Mares2010-01-231-0/+2317
* Added a test case for broken extended capabilitiesMartin Mares2010-01-191-0/+257
* Fix spelling of surpriseEd Swierk2009-08-212-3/+3
* Added a test case for the PCI AF capabilityYu Zhao2009-07-041-0/+29
* Updated test cases from Yu Zhao.Martin Mares2008-12-302-67/+71
* lspci: fix "suprise" typoBjorn Helgaas2008-12-123-3/+3
* Added a test case for the ATS capability.Yu Zhao2008-11-121-0/+298
* Fix spelling of MSI.Martin Mares2008-11-092-2/+2
* Added test cases for new PCIE capabilities.Martin Mares2008-08-262-0/+622
* Added a couple of test cases.Martin Mares2007-10-192-0/+575
* Added decoding of HT MSI capability.Martin Mares2007-08-141-0/+17
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