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| author | zherczeg <zherczeg@6239d852-aaf2-0410-a92c-79f79f948069> | 2016-07-01 08:56:59 +0000 |
|---|---|---|
| committer | zherczeg <zherczeg@6239d852-aaf2-0410-a92c-79f79f948069> | 2016-07-01 08:56:59 +0000 |
| commit | 987102fcb0b726a1f29c9ed3e52c3839ebe372cd (patch) | |
| tree | bd61d01135ae8d4f454020039051bbdeee9d6041 /src/pcre2_jit_compile.c | |
| parent | 0a7a393d707706b82546ac4f616e4c6eed3c37d7 (diff) | |
| download | pcre2-987102fcb0b726a1f29c9ed3e52c3839ebe372cd.tar.gz | |
Fix register overwite in JIT when SSE2 acceleration is enabled.
git-svn-id: svn://vcs.exim.org/pcre2/code/trunk@539 6239d852-aaf2-0410-a92c-79f79f948069
Diffstat (limited to 'src/pcre2_jit_compile.c')
| -rw-r--r-- | src/pcre2_jit_compile.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/pcre2_jit_compile.c b/src/pcre2_jit_compile.c index c98f977..8dea90a 100644 --- a/src/pcre2_jit_compile.c +++ b/src/pcre2_jit_compile.c @@ -4027,12 +4027,12 @@ sljit_emit_op_custom(compiler, instruction, 4); if (load_twice) { - OP1(SLJIT_MOV, TMP3, 0, TMP2, 0); + OP1(SLJIT_MOV, RETURN_ADDR, 0, TMP2, 0); instruction[3] = 0xc0 | (tmp2_ind << 3) | 1; sljit_emit_op_custom(compiler, instruction, 4); OP2(SLJIT_OR, TMP1, 0, TMP1, 0, TMP2, 0); - OP1(SLJIT_MOV, TMP2, 0, TMP3, 0); + OP1(SLJIT_MOV, TMP2, 0, RETURN_ADDR, 0); } OP2(SLJIT_ASHR, TMP1, 0, TMP1, 0, TMP2, 0); |