diff options
| -rw-r--r-- | TSRM/TSRM.c | 5 | ||||
| -rw-r--r-- | ext/opcache/config.m4 | 3 | ||||
| -rw-r--r-- | ext/opcache/jit/zend_jit_x86.dasc | 18 |
3 files changed, 25 insertions, 1 deletions
diff --git a/TSRM/TSRM.c b/TSRM/TSRM.c index 2632543621..132dc05c65 100644 --- a/TSRM/TSRM.c +++ b/TSRM/TSRM.c @@ -764,7 +764,10 @@ TSRM_API void *tsrm_get_ls_cache(void) /* Returns offset of tsrm_ls_cache slot from Thread Control Block address */ TSRM_API size_t tsrm_get_ls_cache_tcb_offset(void) {/*{{{*/ -#if defined(__x86_64__) && defined(__GNUC__) +#if defined(__APPLE__) && defined(__x86_64__) + // TODO: Implement support for fast JIT ZTS code ??? + return 0; +#elif defined(__x86_64__) && defined(__GNUC__) size_t ret; asm ("movq _tsrm_ls_cache@gottpoff(%%rip),%0" diff --git a/ext/opcache/config.m4 b/ext/opcache/config.m4 index 69ee93c872..479f0531c4 100644 --- a/ext/opcache/config.m4 +++ b/ext/opcache/config.m4 @@ -46,6 +46,9 @@ if test "$PHP_OPCACHE" != "no"; then echo 'int i;' > conftest.$ac_ext if AC_TRY_EVAL(ac_compile); then case `/usr/bin/file conftest.o` in + *"Mach-O 64-bit"*) + DASM_FLAGS="-D X64APPLE=1 -D X64=1" + ;; *64-bit*) DASM_FLAGS="-D X64=1" ;; diff --git a/ext/opcache/jit/zend_jit_x86.dasc b/ext/opcache/jit/zend_jit_x86.dasc index 5023db62da..38e2e77800 100644 --- a/ext/opcache/jit/zend_jit_x86.dasc +++ b/ext/opcache/jit/zend_jit_x86.dasc @@ -175,6 +175,14 @@ static void* dasm_labels[zend_lb_MAX]; | mov reg, aword [0x2c] | mov reg, aword [reg + tsrm_tls_index] | mov reg, aword [reg + tsrm_tls_offset] +| .elif X64APPLE +| gs +|| if (tsrm_ls_cache_tcb_offset) { +| mov reg, aword [tsrm_ls_cache_tcb_offset] +|| } else { +| mov reg, aword [tsrm_tls_index] +| mov reg, aword [reg + tsrm_tls_offset] +|| } | .elif X64 | fs || if (tsrm_ls_cache_tcb_offset) { @@ -2563,6 +2571,16 @@ static int zend_jit_setup(void) return FAILURE; } } while(0); +# elif defined(__APPLE__) && defined(__x86_64__) + tsrm_ls_cache_tcb_offset = tsrm_get_ls_cache_tcb_offset(); + if (tsrm_ls_cache_tcb_offset == 0) { + size_t *ti; + __asm__( + "leaq __tsrm_ls_cache(%%rip),%0" + : "=r" (ti)); + tsrm_tls_offset = ti[2]; + tsrm_tls_index = ti[1] * 8; + } # elif defined(__GNUC__) && defined(__x86_64__) tsrm_ls_cache_tcb_offset = tsrm_get_ls_cache_tcb_offset(); if (tsrm_ls_cache_tcb_offset == 0) { |