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author | Andres Freund <andres@anarazel.de> | 2022-12-01 18:46:55 -0800 |
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committer | Andres Freund <andres@anarazel.de> | 2022-12-01 18:46:55 -0800 |
commit | e0f0e08e17a6186ce299ed8a4385a7a486f304ed (patch) | |
tree | 2fa17957a3766ff2deadbeeabd1fbe5b724d94d2 /configure | |
parent | 5e73a6048849bd7bda4947e39570b9011734114d (diff) | |
download | postgresql-e0f0e08e17a6186ce299ed8a4385a7a486f304ed.tar.gz |
autoconf: Unify CFLAGS_SSE42 and CFLAGS_ARMV8_CRC32C
Until now we emitted the cflags to build the CRC objects into architecture
specific variables. That doesn't make a whole lot of sense to me - we're never
going to target x86 and arm at the same time, so they don't need to be
separate variables.
It might be better to instead continue to have CFLAGS_SSE42 /
CFLAGS_ARMV8_CRC32C be computed by PGAC_ARMV8_CRC32C_INTRINSICS /
PGAC_SSE42_CRC32_INTRINSICS and then set CFLAGS_CRC based on those. But it
seems unlikely that we'd need other sets of CRC specific flags for those two
architectures at the same time.
This simplifies the upcoming meson PGXS compatibility.
Reviewed-by: Peter Eisentraut <peter.eisentraut@enterprisedb.com>
Discussion: https://postgr.es/m/20221005200710.luvw5evhwf6clig6@awork3.anarazel.de
Diffstat (limited to 'configure')
-rwxr-xr-x | configure | 19 |
1 files changed, 9 insertions, 10 deletions
@@ -645,8 +645,7 @@ MSGMERGE MSGFMT_FLAGS MSGFMT PG_CRC32C_OBJS -CFLAGS_ARMV8_CRC32C -CFLAGS_SSE42 +CFLAGS_CRC LIBOBJS OPENSSL ZSTD @@ -17957,7 +17956,7 @@ fi # # First check if the _mm_crc32_u8 and _mm_crc32_u64 intrinsics can be used # with the default compiler flags. If not, check if adding the -msse4.2 -# flag helps. CFLAGS_SSE42 is set to -msse4.2 if that's required. +# flag helps. CFLAGS_CRC is set to -msse4.2 if that's required. { $as_echo "$as_me:${as_lineno-$LINENO}: checking for _mm_crc32_u8 and _mm_crc32_u32 with CFLAGS=" >&5 $as_echo_n "checking for _mm_crc32_u8 and _mm_crc32_u32 with CFLAGS=... " >&6; } if ${pgac_cv_sse42_crc32_intrinsics_+:} false; then : @@ -17992,7 +17991,7 @@ fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $pgac_cv_sse42_crc32_intrinsics_" >&5 $as_echo "$pgac_cv_sse42_crc32_intrinsics_" >&6; } if test x"$pgac_cv_sse42_crc32_intrinsics_" = x"yes"; then - CFLAGS_SSE42="" + CFLAGS_CRC="" pgac_sse42_crc32_intrinsics=yes fi @@ -18031,13 +18030,12 @@ fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $pgac_cv_sse42_crc32_intrinsics__msse4_2" >&5 $as_echo "$pgac_cv_sse42_crc32_intrinsics__msse4_2" >&6; } if test x"$pgac_cv_sse42_crc32_intrinsics__msse4_2" = x"yes"; then - CFLAGS_SSE42="-msse4.2" + CFLAGS_CRC="-msse4.2" pgac_sse42_crc32_intrinsics=yes fi fi - # Are we targeting a processor that supports SSE 4.2? gcc, clang and icc all # define __SSE4_2__ in that case. cat confdefs.h - <<_ACEOF >conftest.$ac_ext @@ -18064,7 +18062,7 @@ rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext # # First check if __crc32c* intrinsics can be used with the default compiler # flags. If not, check if adding -march=armv8-a+crc flag helps. -# CFLAGS_ARMV8_CRC32C is set if the extra flag is required. +# CFLAGS_CRC is set if the extra flag is required. { $as_echo "$as_me:${as_lineno-$LINENO}: checking for __crc32cb, __crc32ch, __crc32cw, and __crc32cd with CFLAGS=" >&5 $as_echo_n "checking for __crc32cb, __crc32ch, __crc32cw, and __crc32cd with CFLAGS=... " >&6; } if ${pgac_cv_armv8_crc32c_intrinsics_+:} false; then : @@ -18101,7 +18099,7 @@ fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $pgac_cv_armv8_crc32c_intrinsics_" >&5 $as_echo "$pgac_cv_armv8_crc32c_intrinsics_" >&6; } if test x"$pgac_cv_armv8_crc32c_intrinsics_" = x"yes"; then - CFLAGS_ARMV8_CRC32C="" + CFLAGS_CRC="" pgac_armv8_crc32c_intrinsics=yes fi @@ -18142,13 +18140,14 @@ fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $pgac_cv_armv8_crc32c_intrinsics__march_armv8_apcrc" >&5 $as_echo "$pgac_cv_armv8_crc32c_intrinsics__march_armv8_apcrc" >&6; } if test x"$pgac_cv_armv8_crc32c_intrinsics__march_armv8_apcrc" = x"yes"; then - CFLAGS_ARMV8_CRC32C="-march=armv8-a+crc" + CFLAGS_CRC="-march=armv8-a+crc" pgac_armv8_crc32c_intrinsics=yes fi fi + # Select CRC-32C implementation. # # If we are targeting a processor that has Intel SSE 4.2 instructions, we can @@ -18176,7 +18175,7 @@ if test x"$USE_SLICING_BY_8_CRC32C" = x"" && test x"$USE_SSE42_CRC32C" = x"" && USE_SSE42_CRC32C_WITH_RUNTIME_CHECK=1 else # Use ARM CRC Extension if available. - if test x"$pgac_armv8_crc32c_intrinsics" = x"yes" && test x"$CFLAGS_ARMV8_CRC32C" = x""; then + if test x"$pgac_armv8_crc32c_intrinsics" = x"yes" && test x"$CFLAGS_CRC" = x""; then USE_ARMV8_CRC32C=1 else # ARM CRC Extension, with runtime check? |