Improve SystemVerilog class/endclass lexer rules (#1471)

The class looks like:

class class_identifier [#(param_decls)] [extends class_identifier #(params)];
    ...
endclass [: class_identifier]

Using the same Java convention of Keyword.Declaration and Name.Class.

Add a test_systemverilog_classes unit test to test_hdl.

1 files changed, 10 insertions, 8 deletions

diff --git a/pygments/lexers/hdl.py b/pygments/lexers/hdl.py
index 61d07ba6..a44ff9e5 100644
--- a/pygments/lexers/hdl.py
+++ b/pygments/lexers/hdl.py
@@ -191,15 +191,15 @@ class SystemVerilogLexer(RegexLexer):
                 'always_latch', 'and', 'assert', 'assign', 'assume', 'automatic',
                 'before', 'begin', 'bind', 'bins', 'binsof', 'break', 'buf',
                 'bufif0', 'bufif1', 'case', 'casex', 'casez', 'cell',
-                'checker', 'class', 'clocking', 'cmos', 'config',
+                'checker', 'clocking', 'cmos', 'config',
                 'constraint', 'context', 'continue', 'cover', 'covergroup',
                 'coverpoint', 'cross', 'deassign', 'default', 'defparam', 'design',
                 'disable', 'do', 'edge', 'else', 'end', 'endcase',
-                'endchecker', 'endclass', 'endclocking', 'endconfig', 'endfunction',
+                'endchecker', 'endclocking', 'endconfig', 'endfunction',
                 'endgenerate', 'endgroup', 'endinterface', 'endmodule', 'endpackage',
                 'endprimitive', 'endprogram', 'endproperty', 'endsequence',
                 'endspecify', 'endtable', 'endtask', 'enum', 'eventually',
-                'expect', 'export', 'extends', 'extern', 'final', 'first_match',
+                'expect', 'export', 'extern', 'final', 'first_match',
                 'for', 'force', 'foreach', 'forever', 'fork', 'forkjoin', 'function',
                 'generate', 'genvar', 'global', 'highz0', 'highz1', 'if', 'iff',
                 'ifnone', 'ignore_bins', 'illegal_bins', 'implies', 'implements', 'import',
@@ -230,6 +230,13 @@ class SystemVerilogLexer(RegexLexer):
                 suffix=r'\b'),
              Keyword),
 
+            (r'(class)(\s+)([a-zA-Z_]\w*)',
+             bygroups(Keyword.Declaration, Text, Name.Class)),
+            (r'(extends)(\s+)([a-zA-Z_]\w*)',
+             bygroups(Keyword.Declaration, Text, Name.Class)),
+            (r'(endclass\b)((\s*)(:)(\s*)([a-zA-Z_]\w*))?',
+             bygroups(Keyword.Declaration, None, Text, Punctuation, Text, Name.Class)),
+
             (words((
                 # Variable types
                 'bit', 'byte', 'chandle', 'const', 'event', 'int', 'integer',
@@ -331,15 +338,10 @@ class SystemVerilogLexer(RegexLexer):
                 ), suffix=r'\b'),
              Name.Builtin),
 
-            (r'(class)(\s+)', bygroups(Keyword, Text), 'classname'),
-
             (r'[a-zA-Z_]\w*:(?!:)', Name.Label),
             (r'\$?[a-zA-Z_]\w*', Name),
             (r'\\(\S+)', Name),
         ],
-        'classname': [
-            (r'[a-zA-Z_]\w*', Name.Class, '#pop'),
-        ],
         'string': [
             (r'"', String, '#pop'),
             (r'\\([\\abfnrtv"\']|x[a-fA-F0-9]{2,4}|[0-7]{1,3})', String.Escape),