Add SystemVerilog (IEEE 1800-2012) keywords (#1436)

* Add SystemVerilog (IEEE 1800-2012) keywords

See Table 22-6 -- IEEE 1800-2012 additional reserved keywords

* implements
* interconnect
* nettype
* soft

* Add several SystemVerilog system tasks

See IEEE 1800-2017 Chapter 20:
"Utility system tasks and system functions".

20.2 : $exit $stop
20.3 : $realtime $stime $time
20.4 : $printtimescale $timeformat
20.5 : $bitstoreal $realtobits $bitstoshortreal $shortrealtobits $itor $rtoi
       $signed $unsigned $cast
20.6 : $bits $isunbounded $typename
20.7 : $unpacked_dimensions $dimensions $left $right $low $high $increment $size
20.8 : $clog2 $asin $ln $acos $log10 $atan $exp $atan2 $sqrt $hypot $pow $sinh
       $floor $cosh $ceil $tanh $sin $asinh $cos $acosh $tan $atanh
20.9 : $countbits $countones $onehot $onehot0 $isunknown
20.10: $fatal $error $warning $info
20.12: $asserton $assertoff $assertkill $assertcontrol $assertpasson $assertpassoff
       $assertfailon $assertfailoff $assertnonvacuouson $assertvacuousoff
20.13: $sampled $rose $fell $stable $changed $past $past_gclk $rose_gclk $fell_gclk
       $stable_gclk $changed_gclk $future_gclk $rising_gclk $falling_gclk
       $steady_gclk $changing_gclk
20.14: $coverage_control $coverage_get_max $coverage_get $coverage_merge
       $coverage_save $get_coverage $set_coverage_db_name $load_coverage_db
20.15: $dist_chi_square $dist_erlang $dist_exponential $dist_normal
       $dist_poisson $dist_t $dist_uniform
20.16: $q_initialize $q_add $q_remove $q_full $q_exam
20.17: $async$and$array $async$and$plane $async$nand$array $async$nand$plane
       $async$or$array $async$or$plane $async$nor$array $async$nor$plane
       $sync$and$array $sync$and$plane $sync$nand$array $sync$nand$plane
       $sync$or$array $sync$or$plane $sync$nor$array $sync$nor$plane
20.18: $system

Also:
* Replace '$test' '$plusargs' with '$test$plusargs'.
* Add some comments for the remaining system tasks
* Reorganize tasks into sections (w/ comments), according to spec

Rather than just alphabetize this giant list,
separate them into the sections by spec,
then alphabetize within those sections.
Hopefully, this will make it easier to extend in the future.

* Fix typo: change 'wo' to 'wor'

There is no 'wo' keyword. This was probably supposed to be
'wor', short for "wired OR".

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