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authorChris Drake <cjdrake@users.noreply.github.com>2020-05-26 12:58:05 -0700
committerGitHub <noreply@github.com>2020-05-26 21:58:05 +0200
commit30f060ddfd1aadf41d1b33eae3cde49a6ee57495 (patch)
treebdb4083dd93198d45d7bbcf0f354ddc93cc09cc7 /tests/test_php.py
parent66a949b8e0e5fac42d6006ed66d728808a110633 (diff)
downloadpygments-git-30f060ddfd1aadf41d1b33eae3cde49a6ee57495.tar.gz
Update SystemVerilog literal constants (#1460)
The original implementation was missing some of the more arcane features such as underbars, the character 's' for signed/unsigned, support for spaces before/after the base specifier, capital letter base specifiers (ie 'B 'D 'H), and the 4-state 'xXzZ?' characters. For regular integers, the 'l' and 'L' suffixes are not valid. That is, unlike C, in Verilog '42L' is not a valid int literal. Create a new test that exercises most of the interesting kinds of SystemVerilog numbers. This fixes a couple minor issues with what type of number the lexer returns. For example, Numbers like '42' used to return Integer.Hex, but now return Integer.Decimal.
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