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* Fixup all headers and some more minor problems.2.4.2Georg Brandl2019-05-281-1/+1
* Copyright update.Georg Brandl2017-01-221-1/+1
* VHDL updates (closes #1177)Georg Brandl2016-02-021-5/+12
* Verilog: support $customname (closes #1201)Georg Brandl2016-02-021-4/+4
* Copyright year update.Georg Brandl2015-01-211-1/+1
* Closes #1057: adjust lexer analysis functions; remove too broad analysis for ...Georg Brandl2014-11-091-4/+0
* Simplify charclasses in a few more modulesGeorg Brandl2014-11-061-5/+5
* Protobuf: be conciliatory after keywords, they might be used as identifiersGeorg Brandl2014-11-061-0/+1
* HDL: use words()Georg Brandl2014-11-061-112/+136
* VHDL: fix comment regex; two hyphens always start a commentGeorg Brandl2014-11-061-1/+1
* HDL: PEP8 cleanupGeorg Brandl2014-11-061-17/+16
* Add token type Number.BinDavid Corbett2014-05-191-5/+4
* Overlap due to case insensitive modeGaurav Jain2014-05-151-10/+10
* Replace all occurences of a-zA-Z0-9_ with \wGaurav Jain2014-05-141-3/+3
* Replace all occurences of [a-zA-Z0-9_] with \wGaurav Jain2014-05-141-14/+14
* use versionadded directivesGeorg Brandl2014-01-191-3/+3
* new year in copyright noticeGeorg Brandl2014-01-101-1/+1
* Added and to systemverilog lexer.Aditya Shevade2013-11-091-3/+3
* added language full name in aliases for systemverilog+verilog in lexers/hdl.pyVitaliy Lotorev2013-01-111-2/+2
* Happy new year 2013.Georg Brandl2013-01-091-1/+1
* Move verilog package/import up in match orderTim Hatch2012-03-091-5/+3
* Fix a bunch of minor issues noticed by regexlintTim Hatch2012-03-091-2/+3
* Merge pygments-main with pygments-timTim Hatch2012-02-271-15/+15
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| * Bulk changes to improve many lexers inner workingsTim Hatch2011-03-191-15/+15
* | Add changelog entry for vhdl.Georg Brandl2012-02-081-8/+16
* | Merge with birkenfeld/pygments-mainIgor Kalnitsky2012-02-071-8/+144
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| * | Copyright update.Georg Brandl2012-02-051-1/+1
| * | Closes #734: support the Coq theorem prover.Georg Brandl2012-02-051-0/+4
| * | Changelog entry for SystemVerilog.Georg Brandl2012-02-041-8/+7
| * | Added new SystemVerilog lexer to hdl.py. Fixed integer typo in Verilog lexer...Gordon McGregor2011-10-041-3/+135
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* | Fix some bugs in VHDL Lexer.Igor Kalnitsky2012-02-071-3/+4
* | Added VHDL Lexer.Igor Kalnitsky2012-01-221-2/+79
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* 491: add Verilog lexerthatch2010-05-051-0/+135
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