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| author | Paul McGuire <ptmcg@users.noreply.github.com> | 2018-12-23 21:30:40 -0600 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-12-23 21:30:40 -0600 |
| commit | 4fba64a079016e6ea62d041f19b7eadd081341e8 (patch) | |
| tree | 6c5fdae41cf8b335ff1c64f37856786523e4fd0d /examples/verilogParse.py | |
| parent | 59dfd314c23fd653271bdad37631f0497e8ad748 (diff) | |
| parent | de8326d00dffdb500c02839a98330b869c2457f3 (diff) | |
| download | pyparsing-git-4fba64a079016e6ea62d041f19b7eadd081341e8.tar.gz | |
Merge pull request #55 from jdufresne/ws
Trim trailing white space throughout the project
Diffstat (limited to 'examples/verilogParse.py')
| -rw-r--r-- | examples/verilogParse.py | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/examples/verilogParse.py b/examples/verilogParse.py index 05650df..0c63f19 100644 --- a/examples/verilogParse.py +++ b/examples/verilogParse.py @@ -125,7 +125,7 @@ def Verilog_BNF(): identifier2 = Regex(r"\\\S+").setParseAction(lambda t:t[0][1:]).setName("escapedIdent")#.setDebug()
identifier = identifier1 | identifier2
assert(identifier2 == r'\abc')
-
+
hexnums = nums + "abcdefABCDEF" + "_?"
base = Regex("'[bBoOdDhH]").setName("base")
basedNumber = Combine( Optional( Word(nums + "_") ) + base + Word(hexnums+"xXzZ"),
@@ -557,10 +557,10 @@ def Verilog_BNF(): port = portExpr | Group( ( DOT + identifier + LPAR + portExpr + RPAR ) )
moduleHdr = Group ( oneOf("module macromodule") + identifier +
- Optional( LPAR + Group( Optional( delimitedList(
- Group(oneOf("input output") +
+ Optional( LPAR + Group( Optional( delimitedList(
+ Group(oneOf("input output") +
(netDecl1Arg | netDecl2Arg | netDecl3Arg) ) |
- port ) ) ) +
+ port ) ) ) +
RPAR ) + SEMI ).setName("moduleHdr")
module = Group( moduleHdr +
@@ -710,7 +710,7 @@ else: #~ lp = LineProfiler(ParseResults.__init__)
main()
-
+
#~ lp.print_stats()
#~ import hotshot
#~ p = hotshot.Profile("vparse.prof",1,1)
|