- create tag for 2.5-rc1release0_2

- fix name of old 0.2 tag

6 files changed, 46 insertions, 163 deletions

diff --git a/pyparallel/CHANGES.txt b/pyparallel/CHANGES.txt
index 5ed7b95..94b0269 100644
--- a/pyparallel/CHANGES.txt
+++ b/pyparallel/CHANGES.txt
@@ -2,8 +2,4 @@ Version 0.1     29 Jul 2002
     added to CVS
 
 Version 0.2     27 Jan 2005
-    Windows version now using ctypes
-
-Version ...     ...
-    add setDataDir to Windows backend
-    [SF 2785532] add getData for ppdev backend
+    Windows version now using ctypes
\ No newline at end of file
diff --git a/pyparallel/examples/lcd.py b/pyparallel/examples/lcd.py
index 8e1c66b..b56c2a5 100644
--- a/pyparallel/examples/lcd.py
+++ b/pyparallel/examples/lcd.py
@@ -5,7 +5,7 @@
 # this is distributed under a free software license, see license.txt
 
 import sys, time
-sys.path.insert(0, '..')
+sys.path.append('..')
 import parallel
 
 LCDON           = 0x01 #0x00000001 Switch on  display
@@ -31,8 +31,9 @@ LCD_D6          = 1<<6
 LCD_D7          = 1<<7
 
 
-class FourBitIO(object):
+class LCD:
     def __init__(self):
+        self.p = parallel.Parallel()
         self.data = 0
         
         self.out(0)                 #reset pins
@@ -96,69 +97,6 @@ class FourBitIO(object):
         self.toggleE()              #toggle LCD_E, the enable pin
         time.sleep(0.001)           #wait until instr is finished
 
-
-class EightBitIO(object):
-    def __init__(self):
-        self.data = 0
-        
-        self.setRS(0)
-        self.setRW(0)
-        self.out(0)                 #reset pins
-        time.sleep(0.050)           #wait more than 30ms
-        #send the reset sequece (3 times the same pattern)
-        self.out(LCD8BITS)          #set 8 bit interface
-        self.toggleE()              #toggle LCD_E, the enable pin
-        time.sleep(0.005)           #wait a bit
-        self.toggleE()              #toggle LCD_E, the enable pin
-        time.sleep(0.005)           #wait a bit
-        self.toggleE()              #toggle LCD_E, the enable pin
-        time.sleep(0.005)           #wait a bit
-        
-        #~ self.instr(LCD2LINES)       #set 2 lines display
-        self.instr(LCDCURSOROFF)    #hide cursor
-        self.instr(LCDCLEAR)        #clear display
-
-    def setRW(self, state):
-        self.p.setAutoFeed(state)
-    
-    def setRS(self, state):
-        self.p.setInitOut(state)
-        
-    def toggleE(self):
-        """toggle enable pin"""
-        self.p.setDataStrobe(1)     #toggle LCD_E, the enable pin
-        #~ time.sleep(0.001)
-        self.p.setDataStrobe(0)     #back to inactive position
-        #~ time.sleep(0.001)
-
-    def out(self, data):
-        """set data to LCD port"""
-        self.data = data
-        self.p.setData(self.data)
-
-    def instr(self, cmd):
-        """send instruction byte to LCD"""
-        self.setRS(0)
-        self.setRW(0)
-        self.out(cmd)
-        self.toggleE()              #toggle LCD_E, the enable pin
-        time.sleep(0.005)           #wait until instr is finished
-
-    def putc(self, c):
-        """send a data byte to the LCD"""
-        self.setRS(1)
-        self.setRW(0)
-        self.out(ord(c))
-        self.toggleE()              #toggle LCD_E, the enable pin
-        time.sleep(0.001)           #wait until instr is finished
-
-
-#~ class HD44780(FourBitIO):
-class HD44780(EightBitIO):
-    def __init__(self):
-        self.p = parallel.Parallel()
-        super(HD44780, self).__init__()
-        
     def write(self, str):
         """write a string to the LCD"""
         for c in str:
@@ -171,7 +109,7 @@ class HD44780(EightBitIO):
         self.instr(LCDLINE1)        #just in case, set cursor to a visible pos
 
 if __name__ == '__main__':
-    lcd = HD44780()
+    lcd = LCD()
     lcd.write("Hello World")
     lcd.instr(LCDLINE2)
     lcd.write("from Python")
diff --git a/pyparallel/parallel/parallelppdev.py b/pyparallel/parallel/parallelppdev.py
index d600c4a..18cc54c 100644
--- a/pyparallel/parallel/parallelppdev.py
+++ b/pyparallel/parallel/parallelppdev.py
@@ -183,21 +183,15 @@ class Parallel:
             self.device = port
         else:
             self.device = "/dev/parport%d" % port
-        self._fd = None
         self._fd = os.open(self.device, os.O_RDWR)
-        try:
-            self.PPEXCL()
-            self.PPCLAIM()
-            self.setDataDir(1)
-            self.setData(0)
-        except IOError:
-            os.close(self._fd)
-            self._fd = None
-            raise
+        self.PPEXCL()
+        self.PPCLAIM()
+        self.setDataDir(1)
+        self.setData(0)
 
     def __del__(self):
+        self.PPRELEASE()
         if self._fd is not None:
-            self.PPRELEASE()
             os.close(self._fd)
 
     def timevalToFloat(self, timeval):
@@ -567,12 +561,8 @@ class Parallel:
         """Sets the states of the data bus line drivers (pins 2-9)"""
         self._data=d
         return self.PPWDATA(d)
-    
-    def getData(self):
-        """Gets the states of the data bus line (pin 2-9)"""
-        return self.PPRDATA()
 
-    # status lines
+    #status lines
     def getInError(self):
         """Returns the level on the nFault pin (15)"""
         return (self.PPRSTATUS() & PARPORT_STATUS_ERROR) != 0
diff --git a/pyparallel/parallel/parallelutil.py b/pyparallel/parallel/parallelutil.py
index 036028e..a1a262a 100644
--- a/pyparallel/parallel/parallelutil.py
+++ b/pyparallel/parallel/parallelutil.py
@@ -1,15 +1,15 @@
 class BitaccessMeta(type):
     """meta class that adds bit access properties to a
     parallel port implementation"""
-
+    
     def __new__(self, classname, bases, classdict):
         klass = type.__new__(self, classname, bases, classdict)
-        # status lines
+        #status lines
         klass.paperOut = property(klass.getInPaperOut, None, "Read the PaperOut signal")
-        # control lines
+        #control lines
         klass.dataStrobe = property(None, klass.setDataStrobe, "Set the DataStrobe signal")
-        # XXX ... other bits
-        # data bits
+        #XXX ... other bits
+        #data bits
         for bit in range(8):
             mask = (1<<bit)
             def getter(self, mask=mask):
@@ -20,7 +20,7 @@ class BitaccessMeta(type):
                 else:
                     self.setData(self.getData() & ~mask)
             setattr(klass, "D%d" % bit, property(getter, setter, "Access databit %d" % bit))
-        # nibbles
+        #nibbles
         for name, shift, width in [('D0_D3', 0, 4), ('D4_D7', 4, 4)]:
             mask = (1<<width) - 1
             def getter(self, shift=shift, mask=mask):
@@ -33,34 +33,34 @@ class BitaccessMeta(type):
 class VirtualParallelPort:
     """provides a virtual parallel port implementation, useful
     for tests and simulations without real hardware"""
-
+    
     __metaclass__ = BitaccessMeta
-
+    
     def __init__(self, port=None):
         self._data = 0
-
+        
     def setData(self, value):
         self._data = value
 
     def getData(self):
         return self._data
 
-    # inputs return dummy value
+    #inputs return dummy value
     def getInPaperOut(self): return self._dummy
-    # ...
-    # outputs just store a tuple with (action, value) pair
+    #...
+    #outputs just store a tuple with (action, value) pair
     def setDataStrobe(self, value): self._last = ('setDataStrobe', value)
-    # ...
+    #...
 
-# testing
+#testing
 if __name__ == '__main__':
     import unittest, sys
-
+    
     class TestBitaccess(unittest.TestCase):
         """Tests a port with no timeout"""
         def setUp(self):
             self.p = VirtualParallelPort()
-
+    
         def testDatabits(self):
             """bit by bit D0..D7"""
             p = self.p
@@ -75,7 +75,7 @@ if __name__ == '__main__':
                 [p.D7, p.D6, p.D5, p.D4, p.D3, p.D2, p.D1, p.D0],
                 [1, 0, 1, 0, 1, 0, 1, 0]
             )
-
+            
         def testDatabitsGroups(self):
             """nibbles D0..D7"""
             p = self.p
@@ -86,39 +86,39 @@ if __name__ == '__main__':
             self.failUnlessEqual(p._data, 0xd0)
             p.D0_D3 = p.D4_D7 = 0xa
             self.failUnlessEqual(p._data, 0xaa)
-            # test bit patterns
+            #test bit patterns
             for x in range(256):
-                # test getting
+                #test getting
                 p._data = x
                 self.failUnlessEqual((p.D4_D7, p.D0_D3), (((x>>4) & 0xf), (x & 0xf)))
-                # test setting
+                #test setting
                 p._data = 0
                 (p.D4_D7, p.D0_D3) = (((x>>4) & 0xf), (x & 0xf))
                 self.failUnlessEqual(p._data, x)
-
+        
         def testStatusbits(self):
             """bit by bit status lines"""
-            # read the property:
+            #read the property:
             self.p._dummy = 0
             self.failUnlessEqual(self.p.paperOut, 0)
-
+            
             self.p._dummy = 1
             self.failUnlessEqual(self.p.paperOut, 1)
-
-            # read only, must not be writable:
+            
+            #read only, must not be writable:
             self.failUnlessRaises(AttributeError, setattr, self.p, 'paperOut', 1)
-
+    
         def testControlbits(self):
             """bit by bit control lines"""
             self.p.dataStrobe = 0
             self.failUnlessEqual(self.p._last, ('setDataStrobe', 0))
             self.p.dataStrobe = 1
             self.failUnlessEqual(self.p._last, ('setDataStrobe', 1))
-
-            # write only, must not be writable:
+            
+            #write only, must not be writable:
             self.failUnlessRaises(AttributeError, getattr, self.p, 'dataStrobe')
-
+            
     sys.argv.append('-v')
     # When this module is executed from the command-line, it runs all its tests
     unittest.main()
-
+ 
\ No newline at end of file
diff --git a/pyparallel/parallel/parallelwin32.py b/pyparallel/parallel/parallelwin32.py
index c8f0d23..5c287cb 100644
--- a/pyparallel/parallel/parallelwin32.py
+++ b/pyparallel/parallel/parallelwin32.py
@@ -58,8 +58,7 @@ os.environ['PATH'] = os.environ['PATH'] + ';' + os.path.abspath(os.path.dirname(
 #python extension in earlier versions of this modules
 _pyparallel = ctypes.windll.simpleio
 #need to initialize giveio on WinNT based systems
-if _pyparallel.init():
-    raise IOError('Could not access the giveio driver which is required on NT based systems.')
+_pyparallel.init()
 
 
 class Parallel:
@@ -77,14 +76,6 @@ class Parallel:
     def setData(self, value):
         _pyparallel.outp(self.dataRegAdr, value)
 
-    def setDataDir( self, level):
-        """set for port as input, clear for output"""
-        if level:
-            self.ctrlReg |= 0x20
-        else:
-            self.ctrlReg &= ~0x20
-        _pyparallel.outp(self.ctrlRegAdr, self.ctrlReg)
-
     # control register output functions
     def setDataStrobe(self, level):
         """data strobe bit"""
@@ -109,7 +100,7 @@ class Parallel:
         else:
             self.ctrlReg = self.ctrlReg & ~0x04
         _pyparallel.outp(self.ctrlRegAdr, self.ctrlReg)
-
+    
     def setSelect(self, level):
         """select bit"""
         if level:
diff --git a/pyparallel/setup.py b/pyparallel/setup.py
index 937923f..749470c 100644
--- a/pyparallel/setup.py
+++ b/pyparallel/setup.py
@@ -1,34 +1,13 @@
 #!/usr/bin/env python
-# setup.py
-try:
-    from setuptools import setup
-except ImportError:
-    print "standart distutils"
-    from distutils.core import setup
-else:
-    print "setuptools"
-import sys
-
-#windows installer:
-# python setup.py bdist_wininst
-
-# patch distutils if it can't cope with the "classifiers" or
-# "download_url" keywords
-if sys.version < '2.2.3':
-    from distutils.dist import DistributionMetadata
-    DistributionMetadata.classifiers = None
-    DistributionMetadata.download_url = None
+from distutils.core import setup
 
 import os
 if os.name == 'nt':
-    print "# set dependedcies for windows version"
     data_files = {'parallel': ['simpleio.dll']}
 else:
-    print "# no dependedcies"
-    data_files = {}
+    data_files = None
 
-setup(
-    name = "pyparallel",
+setup (name = "pyparallel",
     description="Python Parallel Port Extension",
     version="0.2",
     author="Chris Liechti",
@@ -37,16 +16,5 @@ setup(
     packages=['parallel'],
     license="Python",
     long_description="Python Parallel Port Extension for Win32, Linux, BSD",
-    classifiers = [
-        'Development Status :: 4 - Beta',
-        'Intended Audience :: Developers',
-        'License :: OSI Approved :: Python Software Foundation License',
-        'Natural Language :: English',
-        'Operating System :: POSIX',
-        'Operating System :: Microsoft :: Windows',
-        'Programming Language :: Python',
-        'Topic :: Communications',
-        'Topic :: Software Development :: Libraries',
-    ],
     package_data = data_files
 )