1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
|
/*
* Copyright (C) 2011 Apple Inc. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL APPLE INC. OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef DFGFPRInfo_h
#define DFGFPRInfo_h
#if ENABLE(DFG_JIT)
#include <assembler/MacroAssembler.h>
#include <dfg/DFGRegisterBank.h>
namespace JSC { namespace DFG {
typedef MacroAssembler::FPRegisterID FPRReg;
#define InvalidFPRReg ((FPRReg)-1)
#if CPU(X86) || CPU(X86_64)
class FPRInfo {
public:
typedef FPRReg RegisterType;
static const unsigned numberOfRegisters = 6;
// Temporary registers.
static const FPRReg fpRegT0 = X86Registers::xmm0;
static const FPRReg fpRegT1 = X86Registers::xmm1;
static const FPRReg fpRegT2 = X86Registers::xmm2;
static const FPRReg fpRegT3 = X86Registers::xmm3;
static const FPRReg fpRegT4 = X86Registers::xmm4;
static const FPRReg fpRegT5 = X86Registers::xmm5;
#if CPU(X86_64)
// Only X86_64 passes aguments in xmm registers
static const FPRReg argumentFPR0 = X86Registers::xmm0; // fpRegT0
static const FPRReg argumentFPR1 = X86Registers::xmm1; // fpRegT1
static const FPRReg argumentFPR2 = X86Registers::xmm2; // fpRegT2
static const FPRReg argumentFPR3 = X86Registers::xmm3; // fpRegT3
#endif
// On X86 the return will actually be on the x87 stack,
// so we'll copy to xmm0 for sanity!
static const FPRReg returnValueFPR = X86Registers::xmm0; // fpRegT0
// FPRReg mapping is direct, the machine regsiter numbers can
// be used directly as indices into the FPR RegisterBank.
COMPILE_ASSERT(X86Registers::xmm0 == 0, xmm0_is_0);
COMPILE_ASSERT(X86Registers::xmm1 == 1, xmm1_is_1);
COMPILE_ASSERT(X86Registers::xmm2 == 2, xmm2_is_2);
COMPILE_ASSERT(X86Registers::xmm3 == 3, xmm3_is_3);
COMPILE_ASSERT(X86Registers::xmm4 == 4, xmm4_is_4);
COMPILE_ASSERT(X86Registers::xmm5 == 5, xmm5_is_5);
static FPRReg toRegister(unsigned index)
{
return (FPRReg)index;
}
static unsigned toIndex(FPRReg reg)
{
return (unsigned)reg;
}
#ifndef NDEBUG
static const char* debugName(FPRReg reg)
{
ASSERT(reg != InvalidFPRReg);
#if CPU(X86_64)
ASSERT(reg < 16);
static const char* nameForRegister[16] = {
"xmm0", "xmm1", "xmm2", "xmm3",
"xmm4", "xmm5", "xmm6", "xmm7",
"xmm8", "xmm9", "xmm10", "xmm11",
"xmm12", "xmm13", "xmm14", "xmm15"
};
#elif CPU(X86)
ASSERT(reg < 8);
static const char* nameForRegister[8] = {
"xmm0", "xmm1", "xmm2", "xmm3",
"xmm4", "xmm5", "xmm6", "xmm7"
};
#endif
return nameForRegister[reg];
}
#endif
};
#endif
#if CPU(ARM_THUMB2)
class FPRInfo {
public:
typedef FPRReg RegisterType;
static const unsigned numberOfRegisters = 6;
// Temporary registers.
// d7 is use by the MacroAssembler as fpTempRegister.
static const FPRReg fpRegT0 = ARMRegisters::d0;
static const FPRReg fpRegT1 = ARMRegisters::d1;
static const FPRReg fpRegT2 = ARMRegisters::d2;
static const FPRReg fpRegT3 = ARMRegisters::d3;
static const FPRReg fpRegT4 = ARMRegisters::d4;
static const FPRReg fpRegT5 = ARMRegisters::d5;
// ARMv7 doesn't pass arguments in fp registers. The return
// value is also actually in integer registers, for now
// we'll return in d0 for simplicity.
static const FPRReg returnValueFPR = ARMRegisters::d0; // fpRegT0
// FPRReg mapping is direct, the machine regsiter numbers can
// be used directly as indices into the FPR RegisterBank.
COMPILE_ASSERT(ARMRegisters::d0 == 0, d0_is_0);
COMPILE_ASSERT(ARMRegisters::d1 == 1, d1_is_1);
COMPILE_ASSERT(ARMRegisters::d2 == 2, d2_is_2);
COMPILE_ASSERT(ARMRegisters::d3 == 3, d3_is_3);
COMPILE_ASSERT(ARMRegisters::d4 == 4, d4_is_4);
COMPILE_ASSERT(ARMRegisters::d5 == 5, d5_is_5);
static FPRReg toRegister(unsigned index)
{
return (FPRReg)index;
}
static unsigned toIndex(FPRReg reg)
{
return (unsigned)reg;
}
#ifndef NDEBUG
static const char* debugName(FPRReg reg)
{
ASSERT(reg != InvalidFPRReg);
ASSERT(reg < 32);
static const char* nameForRegister[32] = {
"d0", "d1", "d2", "d3",
"d4", "d5", "d6", "d7",
"d8", "d9", "d10", "d11",
"d12", "d13", "d14", "d15"
"d16", "d17", "d18", "d19"
"d20", "d21", "d22", "d23"
"d24", "d25", "d26", "d27"
"d28", "d29", "d30", "d31"
};
return nameForRegister[reg];
}
#endif
};
#endif
typedef RegisterBank<FPRInfo>::iterator fpr_iterator;
} } // namespace JSC::DFG
#endif
#endif
|
