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author | Takashi Kokubun <takashikkbn@gmail.com> | 2022-12-28 13:16:14 -0800 |
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committer | Takashi Kokubun <takashikkbn@gmail.com> | 2023-03-05 22:11:20 -0800 |
commit | 4eb6f1dbb9062097c65077eda7945f791c7e4464 (patch) | |
tree | 48752a68094ab61d060220358ae887e4459a5542 | |
parent | e9535a439b1c6717154a79b86d698cb81c3a7d70 (diff) | |
download | ruby-4eb6f1dbb9062097c65077eda7945f791c7e4464.tar.gz |
Put nil on an appropriate index
-rw-r--r-- | bootstraptest/test_mjit.rb | 4 | ||||
-rw-r--r-- | lib/ruby_vm/mjit/insn_compiler.rb | 2 | ||||
-rw-r--r-- | lib/ruby_vm/mjit/x86_assembler.rb | 27 |
3 files changed, 31 insertions, 2 deletions
diff --git a/bootstraptest/test_mjit.rb b/bootstraptest/test_mjit.rb new file mode 100644 index 0000000000..af5b14e50a --- /dev/null +++ b/bootstraptest/test_mjit.rb @@ -0,0 +1,4 @@ +assert_equal 'true', %q{ + def nil_nil = nil == nil + nil_nil +} diff --git a/lib/ruby_vm/mjit/insn_compiler.rb b/lib/ruby_vm/mjit/insn_compiler.rb index 0626f40777..73a260575e 100644 --- a/lib/ruby_vm/mjit/insn_compiler.rb +++ b/lib/ruby_vm/mjit/insn_compiler.rb @@ -8,7 +8,7 @@ module RubyVM::MJIT # @param ctx [RubyVM::MJIT::Context] # @param asm [RubyVM::MJIT::X86Assembler] def putnil(jit, ctx, asm) - asm.mov([SP], Qnil) + asm.mov([SP, C.VALUE.size * ctx.stack_size], Qnil) ctx.stack_size += 1 KeepCompiling end diff --git a/lib/ruby_vm/mjit/x86_assembler.rb b/lib/ruby_vm/mjit/x86_assembler.rb index c80a95a73a..12f65f5432 100644 --- a/lib/ruby_vm/mjit/x86_assembler.rb +++ b/lib/ruby_vm/mjit/x86_assembler.rb @@ -133,10 +133,35 @@ module RubyVM::MJIT mod_rm: mod_rm(mod: 0b00, rm: reg_code(dst_reg)), # Mod 00: [reg] imm: imm32(src_imm), ) + # MOV r/m64, r64 (Mod 00) + in Symbol => src_reg if r64?(dst_reg) && r64?(src_reg) + # REX.W + 89 /r + # MR: Operand 1: ModRM:r/m (w), Operand 2: ModRM:reg (r) + insn( + prefix: REX_W, + opcode: 0x89, + mod_rm: mod_rm(mod: 0b00, reg: reg_code(src_reg), rm: reg_code(dst_reg)), # Mod 00: [reg] + ) + else + raise NotImplementedError, "mov: not-implemented operands: #{dst.inspect}, #{src.inspect}" end in [Symbol => dst_reg, Integer => dst_disp] - # MOV r/m64, r64 (Mod 01) + # Optimize encoding when disp is 0 + return mov([dst_reg], src) if dst_disp == 0 + case src + # MOV r/m64, imm32 (Mod 01) + in Integer => src_imm if r64?(dst_reg) && imm8?(dst_disp) && imm32?(src_imm) + # REX.W + C7 /0 id + # MI: Operand 1: ModRM:r/m (w), Operand 2: imm8/16/32/64 + insn( + prefix: REX_W, + opcode: 0xc7, + mod_rm: mod_rm(mod: 0b01, rm: reg_code(dst_reg)), # Mod 01: [reg]+disp8 + disp: dst_disp, + imm: imm32(src_imm), + ) + # MOV r/m64, r64 (Mod 01) in Symbol => src_reg if r64?(dst_reg) && imm8?(dst_disp) && r64?(src_reg) # REX.W + 89 /r # MR: Operand 1: ModRM:r/m (w), Operand 2: ModRM:reg (r) |