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| author | Takashi Kokubun <takashikkbn@gmail.com> | 2022-11-02 09:30:48 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-11-02 12:30:48 -0400 |
| commit | 81e84e0a4d348309d5d38311d283d049ffeeb7a2 (patch) | |
| tree | 2235fc0e6bb52db3b4ec8a35601a09c06d3518cf /yjit/src/backend | |
| parent | ee7c031dc46b4e86f889b2f98cb479d79774a446 (diff) | |
| download | ruby-81e84e0a4d348309d5d38311d283d049ffeeb7a2.tar.gz | |
YJIT: Support invokeblock (#6640)
* YJIT: Support invokeblock
* Update yjit/src/backend/arm64/mod.rs
* Update yjit/src/codegen.rs
Co-authored-by: Maxime Chevalier-Boisvert <maximechevalierb@gmail.com>
Diffstat (limited to 'yjit/src/backend')
| -rw-r--r-- | yjit/src/backend/arm64/mod.rs | 8 | ||||
| -rw-r--r-- | yjit/src/backend/x86_64/mod.rs | 1 |
2 files changed, 5 insertions, 4 deletions
diff --git a/yjit/src/backend/arm64/mod.rs b/yjit/src/backend/arm64/mod.rs index 0c784c0bea..ce1dd2e43c 100644 --- a/yjit/src/backend/arm64/mod.rs +++ b/yjit/src/backend/arm64/mod.rs @@ -165,8 +165,8 @@ impl Assembler Opnd::Reg(_) | Opnd::InsnOut { .. } => opnd, Opnd::Mem(_) => split_load_operand(asm, opnd), Opnd::Imm(imm) => { - if imm <= 0 { - asm.load(opnd) + if imm == 0 { + Opnd::Reg(XZR_REG) } else if (dest_num_bits == 64 && BitmaskImmediate::try_from(imm as u64).is_ok()) || (dest_num_bits == 32 && @@ -1352,8 +1352,8 @@ mod tests { asm.test(Opnd::Reg(X0_REG), Opnd::Imm(-7)); asm.compile_with_num_regs(&mut cb, 1); - // Assert that a load and a test instruction were written. - assert_eq!(8, cb.get_write_pos()); + // Assert that a test instruction is written. + assert_eq!(4, cb.get_write_pos()); } #[test] diff --git a/yjit/src/backend/x86_64/mod.rs b/yjit/src/backend/x86_64/mod.rs index ac5ac0fff4..dc5f21221d 100644 --- a/yjit/src/backend/x86_64/mod.rs +++ b/yjit/src/backend/x86_64/mod.rs @@ -93,6 +93,7 @@ impl Assembler vec![ RAX_REG, RCX_REG, + RDX_REG, ] } |