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-rw-r--r--yjit/src/backend/ir.rs4
1 files changed, 2 insertions, 2 deletions
diff --git a/yjit/src/backend/ir.rs b/yjit/src/backend/ir.rs
index df0600b2ff..64e5805d9e 100644
--- a/yjit/src/backend/ir.rs
+++ b/yjit/src/backend/ir.rs
@@ -1094,7 +1094,7 @@ impl Assembler
pub fn compile(self, cb: &mut CodeBlock) -> Vec<u32>
{
#[cfg(feature = "disasm")]
- let start_addr = cb.get_write_ptr().raw_ptr();
+ let start_addr = cb.get_write_ptr();
let alloc_regs = Self::get_alloc_regs();
let gc_offsets = self.compile_with_regs(cb, alloc_regs);
@@ -1102,7 +1102,7 @@ impl Assembler
#[cfg(feature = "disasm")]
if let Some(dump_disasm) = get_option_ref!(dump_disasm) {
use crate::disasm::dump_disasm_addr_range;
- let end_addr = cb.get_write_ptr().raw_ptr();
+ let end_addr = cb.get_write_ptr();
dump_disasm_addr_range(cb, start_addr, end_addr, dump_disasm)
}
gc_offsets