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authorMark Rousskov <mark.simulacrum@gmail.com>2022-11-02 08:01:43 -0400
committerMark Rousskov <mark.simulacrum@gmail.com>2022-11-06 17:21:22 -0500
commitb3242f4f1336165903daf363ca0e234c9a0259b2 (patch)
treebce535e2dd771d34d84ff17bf262fec6f4fa2f70 /library/portable-simd
parent40290505fb0aab2ad673a0caa840fc87a1790338 (diff)
downloadrust-b3242f4f1336165903daf363ca0e234c9a0259b2.tar.gz
Fix rustdoc lints
Diffstat (limited to 'library/portable-simd')
-rw-r--r--library/portable-simd/crates/core_simd/src/intrinsics.rs2
-rw-r--r--library/portable-simd/crates/core_simd/src/ops.rs2
2 files changed, 2 insertions, 2 deletions
diff --git a/library/portable-simd/crates/core_simd/src/intrinsics.rs b/library/portable-simd/crates/core_simd/src/intrinsics.rs
index 962c83a78cb..704e6ed0159 100644
--- a/library/portable-simd/crates/core_simd/src/intrinsics.rs
+++ b/library/portable-simd/crates/core_simd/src/intrinsics.rs
@@ -103,7 +103,7 @@ extern "platform-intrinsic" {
/// val: vector of values to select if a lane is masked
/// ptr: vector of pointers to read from
/// mask: a "wide" mask of integers, selects as if simd_select(mask, read(ptr), val)
- /// note, the LLVM intrinsic accepts a mask vector of <N x i1>
+ /// note, the LLVM intrinsic accepts a mask vector of `<N x i1>`
/// FIXME: review this if/when we fix up our mask story in general?
pub(crate) fn simd_gather<T, U, V>(val: T, ptr: U, mask: V) -> T;
/// llvm.masked.scatter
diff --git a/library/portable-simd/crates/core_simd/src/ops.rs b/library/portable-simd/crates/core_simd/src/ops.rs
index 5a077a469d8..fc1e0bc426d 100644
--- a/library/portable-simd/crates/core_simd/src/ops.rs
+++ b/library/portable-simd/crates/core_simd/src/ops.rs
@@ -40,7 +40,7 @@ macro_rules! unsafe_base {
/// SAFETY: This macro should not be used for anything except Shl or Shr, and passed the appropriate shift intrinsic.
/// It handles performing a bitand in addition to calling the shift operator, so that the result
-/// is well-defined: LLVM can return a poison value if you shl, lshr, or ashr if rhs >= <Int>::BITS
+/// is well-defined: LLVM can return a poison value if you shl, lshr, or ashr if `rhs >= <Int>::BITS`
/// At worst, this will maybe add another instruction and cycle,
/// at best, it may open up more optimization opportunities,
/// or simply be elided entirely, especially for SIMD ISAs which default to this.