blob: 9b7b11ef659aac1bfd0512148d9659ec3883dd65 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
|
// MIR for `unchecked_shl_unsigned_smaller` after PreCodegen
fn unchecked_shl_unsigned_smaller(_1: u16, _2: u32) -> u16 {
debug a => _1; // in scope 0 at $DIR/unchecked_shifts.rs:+0:46: +0:47
debug b => _2; // in scope 0 at $DIR/unchecked_shifts.rs:+0:54: +0:55
let mut _0: u16; // return place in scope 0 at $DIR/unchecked_shifts.rs:+0:65: +0:68
scope 1 (inlined core::num::<impl u16>::unchecked_shl) { // at $DIR/unchecked_shifts.rs:11:7: 11:23
debug self => _1; // in scope 1 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
debug rhs => _2; // in scope 1 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
let mut _3: u16; // in scope 1 at $SRC_DIR/core/src/num/mod.rs:LL:COL
let mut _4: (u32,); // in scope 1 at $SRC_DIR/core/src/num/mod.rs:LL:COL
scope 2 {
}
}
bb0: {
StorageLive(_3); // scope 2 at $SRC_DIR/core/src/num/mod.rs:LL:COL
StorageLive(_4); // scope 2 at $SRC_DIR/core/src/num/mod.rs:LL:COL
_4 = (_2,); // scope 2 at $SRC_DIR/core/src/num/mod.rs:LL:COL
_3 = core::num::<impl u16>::unchecked_shl::conv(move (_4.0: u32)) -> bb1; // scope 2 at $SRC_DIR/core/src/num/mod.rs:LL:COL
// mir::Constant
// + span: $SRC_DIR/core/src/num/mod.rs:LL:COL
// + literal: Const { ty: fn(u32) -> u16 {core::num::<impl u16>::unchecked_shl::conv}, val: Value(<ZST>) }
}
bb1: {
StorageDead(_4); // scope 2 at $SRC_DIR/core/src/num/mod.rs:LL:COL
_0 = unchecked_shl::<u16>(_1, move _3) -> [return: bb2, unwind unreachable]; // scope 2 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
// mir::Constant
// + span: $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
// + literal: Const { ty: unsafe extern "rust-intrinsic" fn(u16, u16) -> u16 {unchecked_shl::<u16>}, val: Value(<ZST>) }
}
bb2: {
StorageDead(_3); // scope 2 at $SRC_DIR/core/src/num/uint_macros.rs:LL:COL
return; // scope 0 at $DIR/unchecked_shifts.rs:+2:2: +2:2
}
}
|
