1 files changed, 59 insertions, 0 deletions
diff --git a/ti/speex_C64_test/speex_C64_test.cmd b/ti/speex_C64_test/speex_C64_test.cmd
new file mode 100644
index 0000000..545e7b4
--- /dev/null
+++ b/ti/speex_C64_test/speex_C64_test.cmd
@@ -0,0 +1,59 @@
+/* Copyright (C) 2005 Psi Systems, Inc.
+   File: speex_C64_test.cmd
+   Linker command file with memory allocation for TI TMS320C6415 processor
+   for use with TI Code Composer (TM) DSP development tools.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions
+   are met:
+   
+   - Redistributions of source code must retain the above copyright
+   notice, this list of conditions and the following disclaimer.
+   
+   - Redistributions in binary form must reproduce the above copyright
+   notice, this list of conditions and the following disclaimer in the
+   documentation and/or other materials provided with the distribution.
+   
+   - Neither the name of the Xiph.org Foundation nor the names of its
+   contributors may be used to endorse or promote products derived from
+   this software without specific prior written permission.
+   
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+   ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+   A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR
+   CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+   EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+   PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+   PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+   LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+   NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+-stack 0x10000
+-heap 0x10000
+
+
+MEMORY 
+{
+   VECRAM       : origin = 0x0,         len = 0x200
+   IPRAM       : origin = 0x200,         len = 0x40000
+   IDRAM       : origin = 0x80000,  len = 0x70000
+}
+
+SECTIONS
+{
+        .vectors > VECRAM
+        .text    > IPRAM
+
+        .bss     > IDRAM
+        .cinit   > IDRAM
+        .const   > IDRAM
+        .far     > IDRAM
+        .stack   > IDRAM
+        .cio     > IDRAM
+        .sysmem  > IDRAM
+        .switch  > IDRAM
+        .myheap  > IDRAM
+}